similar to: Suggestions on register allocation by using reinforcement learning

I'm working on my project for completion undergraduate courses, consisting of an experimental analysis of registers allocation algorithms. For this task, I am using the set of tools from the LLVM project. However, I have read the documentation of the LLVM project and not yet found a way to put the pieces of the puzzle together. So far I know: - As passes work as engage them to LLVM and

Dear LLVM developers, Just as LLVM IR can be read/write via persistent bitcode (*.bc *.ll) files, is there any similar implementation in LLVM to read/write Machine IR (MIR) via a persistent file? If not and I would like to add it (e.g. for ARM or RISC-V), could you direct me materials and/or LLVM source code modules where I should start with? Best Regards, Lele Ma -------------- next part

Hello, I am trying to isolate an assertion failure in if-converter (on PPC) and I generated a textual debuglog with: ``` LLVM_ARGS=-print-before-all -print-module-scope -filter-print-funcs=japi1__require_7687 ``` and after splicing out the the MIR before the if-converter pass I would like to run `llc -march=ppc64le -run-pass=if-converter input.mir` so that I can start minimising the MIR. This

I am confused about the rules for when upper and lower case letters should be used in MIR. As an example our downstream target has upper case letters in its sub-register indices and as a result we cannot import exported MIR without manually 'lower casing' it first which is obviously rather annoying. Looking in https://llvm.org/docs/MIRLangRef.html it is stated that instruction names are

Hi llvm developers, I might be overlooking something, but I think the ARMConstantIsland pass uses the wrong size for the MachineInstrs representing jump tables: Currently, there is the following calculation in doInitialJumpTablePlacement (lib/Target/ARM/ARMConstantIslandPass.cpp:588): ---------------------------------------------------------------------- unsigned Size = JT[JTI].MBBs.size() *

On 4/28/2015 7:13 PM, Alex L wrote: > > > 2015-04-28 16:26 GMT-07:00 Matthias Braun <matze at braunis.de > <mailto:matze at braunis.de>>: > > For that use case it is worth keeping the following things in mind: > - Please try to keep the output of the various dump functions, esp. > MachineInstr::dump(), MachineOperand::dump(), >

2015-04-29 11:40 GMT-07:00 Duncan P. N. Exon Smith <dexonsmith at apple.com>: > > > On 2015-Apr-29, at 06:40, Krzysztof Parzyszek <kparzysz at codeaurora.org> > wrote: > > > > On 4/28/2015 7:13 PM, Alex L wrote: > >> > >> > >> 2015-04-28 16:26 GMT-07:00 Matthias Braun <matze at braunis.de > >> <mailto:matze at

Yes, I have done exactly the same. The wawanalyzer is the same. I changed ARM.h and ARMTargetMachine.cpp in the tager/arm folder. then I make tool/llc and lib folder. On Tue, Nov 17, 2015 at 10:55 AM, John Criswell <jtcriswel at gmail.com> wrote: > On 11/17/15 12:16 AM, fateme Hoseini via llvm-dev wrote: > > Hi, > So, I run my pass in X86 target with llc command and it printed

Hi everyone, I am a LLVM newbie. I need to write a machinefunction pass for my project. This should be an analyzer of the machine code to do some profiling. I have written a couple of function passes for front end, but it seems they are completely different. I searched through forum and llvm documents, but couldn't find anything useful or questions were unanswered. Can anyone reference me to

Valentin, in terms of limitations as Sean pointed out, an important one is that .mir doesn't have MachineFunctionInfo which may result in failure on accesses to global variables due to use of register X2. The verifier considers it an undefined register. Also, it's probably easier to reduce test cases using bugpoint starting from an IR test case. With the code you provided, I get a

> On 2015 Apr 29, at 19:13, Hayden Livingston <halivingston at gmail.com> wrote: > > What is missing in the current textual format that doesn't allow going > all the way to machine code? Nothing. What's missing is the ability to serialize the machine level itself. Since many passes have to run to get from .ll to .s, it's currently hard (impossible?) to test

Hi, I have worked a little on the PBQP register allocator, and it is quite clear (at least to me) that it is not even a serious alternative to RegAllocGreedy at the moment, due to the poor handling of spilling. As Arnaud wrote below, it is not optimizing spilling at all, but rather just spills anything that does not get an assignment. The result is a lot more spill/reload instructions than

My god! I would love a branch predictor! It would simplify many aspects of my register allocator. Second, I am surprised it did not make it into the tree. Since more is being done with register allocation as a while "RegAllocBasic" was just put in, I hope this is looked at again. Do you have a working svn copy? Also, could you send me a copy/link to that '94 paper off the list

Hello Valentin, To generate a mir test case i think the process is to first create an IR file by passing '-S -emit-llvm' to clang, then you can feed that file into llc and use stop-before to get the mir just before the if-converter pass, eg: `llc -stop-before=if-converter -simplify-mir -o test.mir test.ll`. Also there is a MIR language reference: https://llvm.org/docs/MIRLangRef.html

Hi Matthias, Thanks a lot for the project. Could you put it in the google doc below? I'd appreciate if you could follow more-or-less the format. Are you going to be the mentor. Cheers, Vassil On 06/02/17 19:29, Matthias Braun wrote: > Here's another one: > > = Improve code generation testing = > > After instruction selection LLVM uses the MI (Machine Instruction)

Hi.... I have a question about how to increase my memory size, could someone answer it for me?? I am using Bioconductor in R to calculate gene expression values with mas5, dchip, and mas4. I have only 18 samples, all from Affymetrix U133A Plus 2 arrays, which has ~54,000 genes. My machine equipments are: CPU P4 3.0GHz, and 1GM RAM. Somehow when I was running mas5 in R, it always showed the error

Dear John, Thank you so much for your help. I looked at those documents. Could you kindly answer the following questions: Does it mean that I have to make my own backend target in order to write a machine pass even if I want to run a simple machinefunction pass? for example,if I want my pass to get MIPS instructions as an input, I have to copy all the files from mips target and add a file to it

Hi, So, I run my pass in X86 target with llc command and it printed out "hello****". Now I am trying to do the same pass for ARM target. So I did exactly what I did for X86 as mentioned in my previous posts. When I run the following command: llc -march=arm test.ll -o test nothing prints out. I did the same for MIPS target too and I got no result. Can anyone tell me what I'm doing

On 6/15/2018 11:58 AM, Muhui Jiang wrote: > Is it possible to dump both the frame setup/cleanup MIR and the MIR I > have at this moment? You can dump the MIR after each pass with -mllvm -print-after-all. Look for "Prologue/Epilogue Insertion". -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

You said it was expensive, but if you had to put a big-o estimate on it, what would it be? -Thanks Jeff Kunkel On Tue, Nov 2, 2010 at 8:54 PM, Andrei Alvares <logytech at gmail.com> wrote: > Hello Jeff, > > On Tue, Nov 2, 2010 at 9:17 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote: > > My god! I would love a branch predictor! It would simplify many aspects > of >