similar to: TableGen: spring cleaning, new features for "functional programming"

Displaying 20 results from an estimated 10000 matches similar to: "TableGen: spring cleaning, new features for "functional programming""

2018 Mar 14
0
TableGen: spring cleaning, new features for "functional programming"
Hi Nicolai, if you're open to it, I'd like suggest another smallish cleanup in libTablegen, namely doing something about the layering. Basicly what bit me a few times is that there is a `Main.cpp` file. This particular file adds CLI options such as -o, -d, -I. So if you build some out-of-tree tool and happen to link against `all` components because you're lazy, there is a high
2018 Feb 21
4
TableGen: spring cleaning, new features for "functional programming"
Hi Artem, Thank you for your encouraging reply :) I have now cleaned up the first batch of changes and put them on Phabricator here: https://reviews.llvm.org/D43552 I've tried to keep individual changes small, and I've verified with `git rebase -x` that the build is good after each change. This first batch does not cause any changes in backend's generated files. [snip]>
2018 Mar 14
0
TableGen: spring cleaning, new features for "functional programming"
Nicolai, I want to say huge thank you for your improvements to tablegen. While it's still far from perfect, I now have a hope that one day I'll be able to *just write* something in tablegen, as opposed to constantly struggling to trick tablegen into doing what I need it to do. Thank you. --Artem On Wed, Feb 21, 2018 at 2:48 AM Nicolai Hähnle <nhaehnle at gmail.com> wrote: >
2018 Feb 20
0
TableGen: spring cleaning, new features for "functional programming"
On Mon, Feb 19, 2018 at 11:26 AM Nicolai Hähnle <nhaehnle at gmail.com> wrote: > Hi all, > > While working on some features for the AMDGPU backend -- specifically, > explicit address components for image intrinsics, which involves > generating both > > (a) a lot of intrinsics with different but somewhat regular parameter > types, and > > (b) the patterns to
2020 Aug 04
2
TableGen trace facility
Are all the records collected as they are parsed, with template parameter substitution and lets, and *then*, after all records are collected, a "pass" is made to calculate the inter-field expressions? Once I understand this, I will add a section to the new guide to explain it. I presume it is the case that this behavior should be publicized. It also appears to be the case that a record
2020 Aug 04
3
TableGen trace facility
Yes, I understand the problem. To be more useful, TableGen would have to carry the traces along with the classes and records and (re)display the values while the substitutions are being made. I'm writing a new Programmer's Guide for TableGen and have been digging into the parse-time versus substitution-time issue. I haven't found a document that makes it clear. Can you give a quick
2020 Mar 13
3
Why MachineBasicBlcok doesn't have transferPredecessors() ?
for example I want to insert a new machine bb “before” a specific machine bb. or split a mbb and keep the later one as the original one. (to keep the label/Blackadder's correct t) (or keep other property of mbb) so I need to transfer the original mbb's predecessor to the new mbb. Nicolai Hähnle <nhaehnle at gmail.com> 於 2020年3月13日 週五 23:57 寫道: > On Fri, Mar 13, 2020 at
2020 Jun 24
4
[RFC] `opt-out` attribute list for intrinsics
Hi all, A while back we started annotating intrinsics with new attributes ( https://reviews.llvm.org/D65377) After some discussion it was decided it would be good to have an `opt-out` attribute list for intrinsics. Some attributes that can be added to the list could be: nosync, nofree, nounwind, willreturn For now, there are 2 approaches: 1. Filtering opt-out attributes in tablegen source (
2018 Nov 30
2
[RFC] Tablegen-erated GlobalISel Combine Rules
> On Nov 29, 2018, at 02:02, Nicolai Hähnle <nhaehnle at gmail.com> wrote: > > On 27.11.18 19:01, Daniel Sanders wrote: >> ...Continued from the other email >> _Removing the defs section_ >> We can potentially infer quite a lot of the defs section but it requires both a complicated ruleset and that tblgen spends processing time doing the inferencing. That
2020 Oct 13
5
Manipulating DAGs in TableGen
On Tue, Oct 13, 2020 at 10:47 AM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote: > What do you guys think about the below enhancements? > > 5. !getdagrestype(dag [, index]) - Returns type of result value. If the DAG computes multiple values then return type of 'index'th result. > > 6. !setdagrestype(dag target_dag, type T [, index]) - Set return type of
2020 Aug 09
4
Another possible tracing feature for TableGen
I had another idea for a TableGen tracing feature and would like some feedback. It's quite possible I'm on the wrong track here and that improved backend tracing is what folks really need. The idea is to add a -trace option to the tblgen command line. With it you can list one or more record names. TableGen would produce a detailed trace of how the record is built: class inheritances,
2018 Nov 09
3
[RFC] Tablegen-erated GlobalISel Combine Rules
Hi Nicolai, Le ven. 9 nov. 2018 à 09:24, Nicolai Hähnle <nhaehnle at gmail.com> a écrit : > > Hi Quentin, > > On 09.11.18 18:16, Quentin Colombet via llvm-dev wrote: > > Disclaimer: Haven't read the proposal yet. > > > >> TL;DR: We're planning to define GlobalISel Combine Rules using MIR syntax with a few bits glued on to interface with the
2020 Jul 13
2
[Beginner] Understanding Tablegen language
Hi, I am new to LLVM and I find TableGen language really cryptic. The reference manual to the language is not helpful either. I can look at the existing .td file and reverse engineer but I am looking for a detailed manual. Specifically, I have below questions: 1. What is a basic syntax for writing a dag? From the lang ref manual I can see that its something like operator followed by ArgList which
2020 Mar 02
3
TableGen Instruction class Uses and Defs
Hello LLVM-Dev, I understand that Uses and Defs are for implicit registers. Uses is defined as for using non-operand registers and Defs is defined as for modifying non-operand registers. For example, for compare and compare with carry instructions, is my understanding correct that the instructions should be defined as described below? Considering that the carry flag is part of the status
2020 Feb 05
2
Eliminate some two entry PHI nodes - SimplifyCFG
Conditional on the target supporting cmov? Though that's probably not optimal. On Wed, Feb 5, 2020, 7:47 AM Nicolai Hähnle <nhaehnle at gmail.com> wrote: > Hi Ryan, > > On Mon, Feb 3, 2020 at 7:08 PM Ryan Taylor via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > SimplifyCFG FoldTwoEntryPhiNode looks to simplify all 2 entry phi nodes > in a block, if it
2018 Feb 28
0
TableGen: spring cleaning, new features for "functional programming"
Hi Nicolai, Thanks for your work, and I do enjoy reading your blog posts. It would be nice adding links to your post somewhere on existing tablegen documents, or even better, you can improve them (for clarity and readability :p). Cheers, chenwj -- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj -------------- next part -------------- An HTML attachment was scrubbed... URL:
2019 Jun 06
3
[RFC] Expressing preserved-relations between passes from different modules (was: Re: Linker issue)
Any comments at all on this? Chandler perhaps? I've since dug a bit further, and it seems like the template-based solution wouldn't work anyway because DLL loading on Windows can't do the required commoning. So the general approach taken in https://reviews.llvm.org/D62802 seems to be the only technically viable path forward, though it would still be good to get an outside look at the
2018 Aug 22
2
Condition code in DAGCombiner::visitFADDForFMACombine?
On 22.08.2018 17:52, Ryan Taylor wrote: > This is probably going to effect on other backends and break llvm-lit > for them? Very likely, yes. Can you take a look at how big the fallout is? This might give us a hint about what other frontends might expect, and who needs to be involved in the discussion (if one is needed). Cheers, Nicolai > > On Wed, Aug 22, 2018 at 11:41 AM
2018 Nov 09
2
[RFC] Tablegen-erated GlobalISel Combine Rules
Hi Daniel, Disclaimer: Haven't read the proposal yet. > TL;DR: We're planning to define GlobalISel Combine Rules using MIR syntax with a few bits glued on to interface with the algorithm and escape into C++ when we need to. Eventually, ISel rules may follow suit. I would rather avoid adding a dependency on yet another tablegen backend to the project unless we are confident it is
2017 Aug 21
2
Extending TableGen's 'foreach' to work with 'multiclass' and 'defm'
I have been reading the “RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends” topic with considerable interest. This is an approach I have been considering for taming our own large instruction set, and it looks like it structures our descriptions better than the conventional approach we have used so far. However, I have another form of TableGen taming that I