similar to: Suggentions on modeling a micro architecture with per-operand machine model

I have a code generation question for ARM with VFP and NEON. I am generating code for the following function as a test: void FloatingPointTest(float f1, float f2, float f3) { float f4 = f1 * f2; if (f4 > f3) printf("%f\n",f2); else printf("%f\n",f3); } I have tried compiling with: 1. -mfloat-abi=softfp and -mfpu=neon 2.

Hi Florian, I understand you want to discuss the x86_64 micro-architecture levels only in this thread, but it would be nice to have a similar discussion for other architectures. One thing that wasn't clear to me from this proposal is how the glibc dynamic loader checks for the CPU feature flags. This is important for valgrind since it can communicate those through different means. cpuid

On 13.07.2020 09:40, Florian Weimer wrote: > * Richard Biener: >>> 2. I have a library with AVX2 and FMA, which directory should it go? >> >> Eventually GCC/gas can annotate objects with the lowest architecture >> level that is applicable? > > H.J. has patches for ELF program properties. I think > GNU_PROPERTY_X86_ISA_1_NEEDED would convey this information.

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.

Hello, On Wed, 22 Jul 2020, Mallappa, Premachandra wrote: > > That's deliberate, so that we can use the same x86-* names for 32-bit library selection (once we define matching micro-architecture levels there). > > Understood. > > > If numbers are out, what should we use instead? > > x86-sse4, x86-avx2, x86-avx512? Would that work? > > Yes please, I think

Hi Andy and all, I have a question about per-operand machine model. I am finding some relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST:

* Dongsheng Song: > I fully agree these names (100/101, A/B/C/D) are not very intuitive, I > recommend using isa tags by year (e.g. x64_2010, x64_2014) like the > python's platform tags (e.g. manylinux2010, manylinux2014). I started out with a year number, but that was before the was Level A. Too many new CPUs only fall under level A unfortunately because they do not even have AVX.

On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1,

On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: > Hi Andrew, > > We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models. > > To expand on what JinGu mentioned, our target has explicit ports that are used to read and

On Fri, Jul 10, 2020 at 11:45 PM H.J. Lu via Gcc <gcc at gcc.gnu.org> wrote: > > On Fri, Jul 10, 2020 at 10:30 AM Florian Weimer <fweimer at redhat.com> wrote: > > > > Most Linux distributions still compile against the original x86-64 > > baseline that was based on the AMD K8 (minus the 3DNow! parts, for Intel > > EM64T compatibility). > > > >

* Premachandra Mallappa: > [AMD Public Use] > > Hi Floarian, > >> I'm including a proposal for the levels below. I use single letters for them, but I expect that the concrete implementation of this proposal will use >> names like “x86-100”, “x86-101”, like in the glibc patch referenced above. (But we can discuss other approaches.) > > Personally I am not a big

>Resources and latency are not tied. An instruction is mapped to a scheduling class. A scheduling class is mapped to a set of resources and a per-operand list of latencies. Thanks for your kind explanation. Our heuristic algorithm have needed the latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of

On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote: > > On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: >> >>> Hi Andrew, >>> >>> We are currently using a custom model where

Viswanath Puttagunta wrote: > + SUMM = vdupq_n_f32(0); It kills me that there's no intrinsic for VMOV.F32 d0, #0 (or at least I couldn't find one), so this takes two instructions instead of one. > + /* Consume 4 elements in x vector and 8 elements in y > + * vector. However, the 8'th element in y never really gets > + * touched in this loop. So, if len == 4,

* Richard Biener: > On Wed, Jul 22, 2020 at 10:58 AM Florian Weimer via Gcc <gcc at gcc.gnu.org> wrote: >> >> * Dongsheng Song: >> >> > I fully agree these names (100/101, A/B/C/D) are not very intuitive, I >> > recommend using isa tags by year (e.g. x64_2010, x64_2014) like the >> > python's platform tags (e.g. manylinux2010,

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

We have a two different dimensions for each instruction: slot assignments, and operand timings. These two are unrelated to each other, and also each (or both) can change for any given instruction from one architecture version to the next. The main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using

Hi, What is the best way to model a scheduler for a VLIW in-order architecture? I've looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. I also found this thread from almost 2 years ago: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098763.html At that time it seemed the

> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. > > I