similar to: Undef physical registers?

On Fri, 2019-08-30 at 10:03 -0700, Quentin Colombet wrote: > > On Aug 30, 2019, at 8:31 AM, Jesper Antonsson via llvm-dev < > > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > After dead-mi-elimination I'm experiencing a machine verifier > > failure > > at this virtual subregister write: > > > > %5.sub1 = COPY undef

Hi, I'm with a team using 16-bit bytes for an out-of-tree target. The AsmPrinter framework's implementation of the DWARF debugging format is not very good at distinguishing between target-sized bytes (which is the more common use) and 8-bit-bytes. The DWARF standard itself seems not very good in this regard, actually. So we have had to hack our way around this. I.e., at some call-sites of

Hi, After dead-mi-elimination I'm experiencing a machine verifier failure at this virtual subregister write: %5.sub1 = COPY undef %11 The machine verifier essentially complains that the rest of the register is undefined (a subregister write implies a "read" of the other parts). So the problem is that dead-mi-elimination has removed the previously existing defines of %5.sub0.

A. This RFC outlines a proposal regarding non-8-bit-byte support that got positive reception at a Round Table at EuroLLVM19. The general topic has been brought up several times before and one good overview can be found in a FOSDEM 2017 presentation by Jones and Cook: https://archive.fosdem.org/2017/schedule/event/llvm_16_bit/ In a nutshell, the proposal is for the llvm community

On Thu, 2019-05-02 at 19:54 +0200, Pavel Šnobl wrote: > Hi Jesper, > > thank you for working on this. My company (Codasip) would definitely > be interested in having this feature upstream. I think that this is > actually important for a suprisingly large number of people who > currently have to maintain their changes downstream. I have a couple > of questions and comments:

I just finished coding up a change to how code generation builds machine instructions. The change is in include/llvm/CodeGen/MachineInstrBuilder.h, where when you want to add a register, you have to specify a long list of booleans indicating if it's defined, implicit, killed, dead, or early clobbered. I don't know about you, but it was hard for me to read the source and understand what was

*From: *JF Bastien via llvm-dev <llvm-dev at lists.llvm.org> *Date: *Thu, May 9, 2019 at 1:30 PM *To: *Jesper Antonsson *Cc: *dag at cray.com, llvm-dev at lists.llvm.org I don’t think you have consensus to move forward at this point in time. My > expectation, which I think represents LLVM’s historical approach, is that a > path to full support be planned out before this effort starts.

Thank you for your reply! If liveness of APSR is not tracked, how does the code generator determine whether instructions like cmp are dead code or not? Is it true that, for every use of APSR (such as a conditional branch), the used def (such as cmp, add, etc.) is always in the same basic block? Is it true that APSR is never assumed to live across basic block boundaries? Thank you! Ming Zhang

On Wed, 2019-05-08 at 11:12 -0700, Philip Reames wrote: > On 5/8/19 1:25 AM, Jesper Antonsson wrote: > > On Mon, 2019-05-06 at 15:56 -0700, Philip Reames via llvm-dev > > wrote: > > > On 5/6/19 2:43 AM, Tim Northover via llvm-dev wrote: > > > > On Mon, 6 May 2019 at 10:13, James Courtier-Dutton via llvm-dev > > > > <llvm-dev at lists.llvm.org>

I agree that consensus seems to be missing. There's definitely some assumptions, and more in particular, API and usage assumptions around 8 bit bytes in the backends. Also: How do you plan on keeping these assumptions from creeping back in? -eric On Thu, May 9, 2019 at 10:30 AM JF Bastien via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > On May 9, 2019, at 5:29 AM,

Sorry, this is the part in ARMLoadStoreOptimizer.cpp that creates a LDRD instruction. Ops.pop_back(); Ops.pop_back(); // Form the pair instruction. if (isLd) { MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TII->get(NewOpc)) .addReg(EvenReg, RegState::Define)

Where is the liveness analysis pass? I have been looking for days but cannot find anything. I just want to know transfer variables in and out of basic blocks, that are calculated using simple data flow equations. Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180920/529bce15/attachment.html>

> On Nov 1, 2019, at 3:41 AM, Dmitriy Borisenkov via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > A summary of the discussion so far. > > It seems that there are two possible solutions on how to move forward with non 8 bits byte: > > 1. Commit changes without tests. Chris Lattner, Mikael Holmen, Jeroen Dobbelaere, Jesper Antonsson support this idea. > James Y

The comment in test/CodeGen/X86/branchfolding-undef.mir states that such merging is legal, however doing so can actually generate wrong code: Consider this (valid code): --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 =

On Wed, 2019-10-30 at 15:30 -0700, Chris Lattner via llvm-dev wrote: > > On Oct 30, 2019, at 3:07 AM, Jeroen Dobbelaere via llvm-dev < > > llvm-dev at lists.llvm.org> wrote: > > > > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of JF > > > Bastien via > > > > [..] > > > Is it relevant to any modern compiler

On Mon, 2019-05-06 at 15:56 -0700, Philip Reames via llvm-dev wrote: > > > On 5/6/19 2:43 AM, Tim Northover via llvm-dev wrote: > > On Mon, 6 May 2019 at 10:13, James Courtier-Dutton via llvm-dev > > <llvm-dev at lists.llvm.org> wrote: > > > Although the above is mentioning bytes, looking at the "/ > > > 8" and "& 0x7" makes

Yes, immediately after branch folding the code would still behave the same as the original. At the same time, any subsequent optimization may "exploit" the incorrect liveness information to do something bad. If you add -run-pass if-converter, you'll get: # After If Converter # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs BB#0: %R0<def>

I agree, addressable unit size is probably a better abstraction. However, in the lib/CodeGen directory alone, there's some 785 uses of the word "byte" and a significant fraction of the code that we want to modify is using the byte terminology today. An example of unmodified code from my showcase patch set: assert(!(Shift & 0x7) == 0 && "Shifts not

Hi, I wonder if anyone has any comment on a patch like: diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 65ee3816f84..4780f6f0e59 100644 --- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -243,18 +243,21 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,      if (!VRBase &&

On 13/05/2009, at 02.46, Bill Wendling wrote: > Instead of all of the booleans, you pass in a flag that has bits set > to indicate what state the register is in: > > namespace RegState { > enum { > Define = 0x1, > Implicit = 0x2, > Kill = 0x4, > Dead = 0x8, > EarlyClobber = 0x10, > ImplicitDefine = Implicit |