similar to: [VLIW Scheduler] Itineraries vs. per operand scheduling

> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. > > I

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using

We have a two different dimensions for each instruction: slot assignments, and operand timings. These two are unrelated to each other, and also each (or both) can change for any given instruction from one architecture version to the next. The main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and

> On Nov 9, 2015, at 10:49 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Mon, Nov 9, 2015 at 10:31 AM, Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote: > ----- Original Message ----- > > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > > To:

Microsoft assembler treats mov to EAX as a register, even if there is a global memory also named EAX – meaning the register takes precedence. But here I have a bit of a different situation – I have a global variable, which name happens to match an implicit register or a register that does not exist in the current arch, just in future ones. Microsoft assembler treats these cases as memory

Some targets don't have the problem because they prefix all names with an undercore. Apart from that I am not aware of any solution to the problem of keywords clashing with variable names in intel syntax. - Matthias > On Jul 23, 2015, at 9:18 AM, Reid Kleckner <rnk at google.com> wrote: > > So, there is no prior art for escaping the name of a global symbol with the same name

----- Original Message ----- > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Monday, November 9, 2015 10:09:07 AM > Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries? > > > Anybody? Does anyone at all know how to do it? There is

So, there is no prior art for escaping the name of a global symbol with the same name as a register? If there is, I'd rather we just implement it and leave it at that. We can probably fix the 'flags' case easily in LLVM, but I'd rather not bend over backwards to make ZMM0 be a global name when AVX is disabled. On Thu, Jul 23, 2015 at 9:12 AM, Yatsina, Marina <marina.yatsina at

Linux kernel is using the “asm goto” feature, other projects probably use it as well. I think it provides motivation to support it in LLVM. Regarding the complexity, I believe there is some infrastructure that we can at least partially reuse (the support for “indirectbr” instruction). My focus is adding “asm goto” support, the other things are indeed completely orthogonal and came up in bugs

Asm goto feature was introduces to GCC in order to optimize the support for tracepoints in Linux kernel (it can be used for other things that do nop patching). GCC documentation describes their motivating example here: https://gcc.gnu.org/onlinedocs/gcc-4.8.4/gcc/Extended-Asm.html #define TRACE1(NUM) \ do { \

Hi all, I've encountered an issue with x86 Intel asm syntax when using certain variable names. If you look at the following example, where I try to do a mov to a memory location named "flags2", llvm- mc works fine: >cat test_good.s mov eax, flags2 >llvm-mc.exe -x86-asm-syntax=intel test_good.s -o - .text movl flags2, %eax But if the memory location is

Suppose I have a global variable named 'EAX'. How do Intel assemblers normally escape register names to access such a global variable? On Thu, Jul 23, 2015 at 1:42 AM, Yatsina, Marina <marina.yatsina at intel.com> wrote: > Hi all, > > > > I’ve encountered an issue with x86 Intel asm syntax when using certain > variable names. > > > > If you look at

On Tue, Apr 4, 2017 at 6:07 AM Yatsina, Marina via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Asm goto feature was introduces to GCC in order to optimize the support > for tracepoints in Linux kernel (it can be used for other things that do > nop patching). > > > > GCC documentation describes their motivating example here: > > >

Hi, I wanted to revive this issue of supporting asm goto (Bug 9295<https://bugs.llvm.org/show_bug.cgi?id=9295>). As was already proposed, the best way seems to be introducing new IR. If we're changing the IR, we should probably provide an infrastructure that solves or at least enables future support for things like: 1. MS-style inline asm jmps and goto (Bug

Is there a way to convert between SchedMachineModel and Itineraries? I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would

My two cents: - I think inline assembly should work even if the compiler cannot parse the contents. This would rule out msvc inline assembly (or alternatively put all the parsing and interpretation burden on the frontend), but would work with gcc asm goto which specifies possible targets separately. - Supporting control flow in inline assembly by allowing jumps out of an assembly block seems

So if I use the SchedMachineModel method, can I just skip itineraries? Phil On Wed, Apr 20, 2016 at 12:29 PM, Sergei Larin <slarin at codeaurora.org> wrote: > Target does make a difference. VLIW needs more hand-holding. For what you > are describing it should be fairly simple. > > > > Best strategy – see what other targets do. ARM might be a good start for > generic

Hi Phil. You more or less answered your own question, but let me give you some more info. Maybe it is of use. >From what I understand the SchedMachineModel is the future, although it is not as powerful as itineraries at present. The mi-scheduler is mostly developed around out-of-orders cores, I believe (I love to hear arguments on the contrary). Some of the constraints that can be found in

Hi Rotem, Thank to you, and especially to Marina! The problem gone. I'm a bit interested, what is the reason it worked in Win7, and not in Win8. I've recently used Process Explorer to discover, that the call was to ntdll.dll, which in Win8 is loaded to the totally different address. Best regards, Victor Milovanov Moscow State University graduate student 2012/3/3 Rotem, Nadav

Hi, >From what I can understand from analyzing several *.td files, there are two ways of specifying scheduling information for a specific target, either using SchedWriteRes and InstrItinClass/Data. Specifically looking at ARMScheduleA9.td, I can find both representations and a comment (in the beggining of the file): // This section contains legacy support for itineraries. This is // required