similar to: Subject: How to define vector element type bool in builtin function

Displaying 20 results from an estimated 300 matches similar to: "Subject: How to define vector element type bool in builtin function"

2018 Apr 24
0
Help: How to define vector element type bool (v8i1) in C builtin function
Help: How to define vector element type bool (v8i1) in C builtin function hello everyone,I have defined intrinsic function like this: def int_mips_add_32 : GCCBuiltin<"__builtin_dongxin_add_32">, Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v8i1_ty]>; Then I write a test code : typedef int v4i32 __attribute__ ((vector_size(16))); typedef bool v8i1
2018 Apr 21
0
How to add/use parameter attributes? Troubles with "byval"
I'm unable to figure out how IR attributes can be added via the C++ API. I need to create a function like this:     %1 = call i64 @abi_call_test_tuple_2p(%struct.abi_tuple_2p* byval align 8 %v) Where a structure is being passed by value. I need to add the `byval` attribute somewhere (I'm not clear if this is on the function arguments or the type). I'm also uncertain of why that
2007 Jul 11
1
[LLVMdev] New LLVM C front-end: "clang"
Hi Everyone, I'm happy to say that we just got approval to open source the new C front-end for LLVM we've been working on. The goal of this work is to provide a high quality front-end for LLVM that is built with the same principles as the rest of LLVM (it is built as a set of reusable libraries, integrates well with rest of the LLVM architecture, same license, etc). Among other
2009 Oct 09
3
[LLVMdev] Help with gcc SSE intrinsics
Ok, I've been looking at this for hours and can't figure it out. I know I'm missing something obvious. I've been spending the past few days beefing up the vector support in the C Backend. This should help us debug vector code that's miscompiled. But gcc doesn't like this fragment: ((double *)(&llvm_cbe_r1147))[0u] = (((llvm_cbe_r1146__BITCAST_TEMPORARY.Int64 =
2019 Oct 17
2
Static assert fails when compiler for i386
Hi Devs, Consider below testcase. $cat test.cpp #include <vector> #include<type_traits> typedef int _int4 __attribute__((vector_size(16))); typedef union{ int data[4]; struct {int x, y, z, w;}; _int4 vec; } int4; typedef int4 int3; int main() { static_assert(std::alignment_of<int4>::value <= alignof(max_align_t), "over aligned!"); } $clang++ -m32 error:
2009 Oct 09
0
[LLVMdev] Help with gcc SSE intrinsics
On Oct 9, 2009, at 1:26 PMPDT, David Greene wrote: > Ok, I've been looking at this for hours and can't figure it out. I > know I'm > missing something obvious. > > I've been spending the past few days beefing up the vector support > in the C > Backend. This should help us debug vector code that's miscompiled. > But > gcc doesn't like
2017 Sep 10
2
Question about quad-register
Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing
2011 Jun 30
1
[LLVMdev] sparse typedef int v8qi __attribute__ ((mode(V8QI))) warning
While solving a clang build issue with netpbm10 on fink darwin11, I noticed that clang seems to provide poor error messages compared to llvm-gcc. For llvm-gcc, we get the very helpful warning... libpbm3.c: In function 'packBitsWithMmxSse': libpbm3.c:120: warning: specifying vector types with __attribute__ ((mode)) is deprecated libpbm3.c:120: warning: use __attribute__ ((vector_size))
2012 Feb 14
1
[LLVMdev] question on scalarization
Hi all, I have a backend for an in house architecture, and would like to start working on support for vector datatypes and intrinsics. As I starter I would like to have vector code scalarized, as is done, e.g., for the Mips backend. However, I cannot find a way to force the instruction selector or type legalizer to scalarize the vectors (i.e., vector types and vector ops). Can anyone help me out?
2013 Oct 30
0
[LLVMdev] [AVX512] Inconsistent mask types for intrinsics?
Hey guys, There seems to be an inconsistency between mask operand types for the AVX512 intrinsics. The mask instruction intrinsics expect a v16i1 for the mask operands: > def int_x86_kadd_v16i1 : GCCBuiltin<"__builtin_ia32_kaddw">, > Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty], > [IntrNoMem]>; But other
2009 Sep 04
3
[LLVMdev] TOT opt does not terminate!
The following code causes opt to not terminate! With TOT this morning, and of a week ago: clang foo.c and clang -O1 foo.c work fine. clang -O2 foo.c and clang -O3 foo.c do not terminate. (At least after 10 minutes) If I generate the bit code (clang-cc -emit-llvmbc) and then run: opt -O3 foo.bc it does not terminate. //foo.c int get_id(int); typedef short
2011 Apr 14
2
[LLVMdev] [x86 codegen] 3DNow! intrinsics not behaving as expected.
I finally got all of the 3DNow! instruction intrinsics and builtins into LLVM and Clang, however, while testing them, I've noticed that they produce incorrect results. For example: typedef float V2f __attribute__((vector_size(8))); int main() { V2f dest, a = {1.0, 3.0}, b = {10.0, 3.5}; dest = __builtin_ia32_pfadd(a, b); printf("(%f, %f)\n", dest[0], dest[1]); } Should
2018 Nov 27
2
Vectorizer has trouble with vpmovmskb and store
We should handle this a lot better after r34763 ~Craig On Mon, Nov 26, 2018 at 3:13 PM Craig Topper <craig.topper at gmail.com> wrote: > Here's a quick patch that fixes this. I don't know to avoid it in IR. I > haven't checked any other tests, but it does fix your case. I'll try to put > up a real phabricator tonight or tomorrow. > > diff --git
2016 Jan 28
2
Vectors in Sparc
The following code is causing me problems in the Sparc back-end and I believe it's related to a lot of issues that I have, so I'd love to work out what I need to do to resolve this. I'm currently not making much headway into it. I'm going to try to simplify this to the core problem I can see and hope I haven't missed anything relevant. The original code I have is as follows:
2011 Mar 08
3
[LLVMdev] Vector select/compare support in LLVM
Hello, I started working on adding vector support for the SELECT and CMP instructions in the codegen (bugs: 3384, 1784, 2314).  Currently, the codegen scalarizes vector CMPs into multiple scalar CMPs.  It is easy to add similar scalarization support to the SELECT instruction.  However, using multiple scalar operations is slower than using vector operations. In LLVM, vector-compare operations
2016 Jun 29
0
Question about VectorLegalizer::ExpandStore() with v4i1
Rob, Ahmed, and Jingu, [I'm sorry if my point of view is too x86 centric.] >>the tricky part about fixing it is the need to settle on a memory layout for these vectors >> (packed vs byte per i1; packed would be compatible with AVX512, I think). I agree with Ahmed here, in principle. It's actually more than that, since vector compare in AVX2 and below produces the same
2016 May 25
0
running intrinsics from C code
GCCBuiltin just gives it a name for clang to lookup. Generally they match up with builtins that gcc also implements, but that's not a requirement. If you add a builtin with the same name to the builtin file in clang's include/clang/Basic/Builtins*.def then they will find each other. You can also just add a builtin to clang's builtin file and catch it in clang's
2011 Apr 14
0
[LLVMdev] [x86 codegen] 3DNow! intrinsics not behaving as expected.
On Thu, Apr 14, 2011 at 12:16 PM, Michael Spencer <bigcheesegs at gmail.com> wrote: > I finally got all of the 3DNow! instruction intrinsics and builtins > into LLVM and Clang, however, while testing them, I've noticed that > they produce incorrect results. > > For example: > > typedef float V2f __attribute__((vector_size(8))); > > int main() { >  V2f dest,
2016 Feb 01
2
Question about store with unaligned memory address
Hi Bruce, Thanks for response. I also think it is not good way. Do you have the other ways to legalize it? Thanks, JinGu Kang 2016-02-01 13:11 GMT+00:00 Bruce Hoult <bruce at hoult.org>: > In fact this is a pretty bad legalizing/lowering because you only need to > load and edit for the first and last values in the vector. The other words > are completely replaced and don't
2019 Sep 27
2
Opportunity to split store of shuffled vector.
> I may be missing something obvious, but what is `vector` defined as here? Can you provide a buildable example? Sorry, I should provide a cross-platform version using vector extension of frontend :) `vector int` is a vector extension on PowerPC, which is enabled if you set target to PowerPC platforms. Example below should be successfully compiled in any platform: typedef float v4sf