Displaying 7 results from an estimated 7 matches similar to: "64 bit mask in x86vshuffle instruction"
2017 Aug 26
2
Error in generating Object Code for implemented assembly vector instructions
i want to emit binary code for the following implemented vector assembly
instructions.
P_256B_LOAD_DWORD R_0_R2048b_0, pword ptr [rip + b]
P_256B_LOAD_DWORD R_0_R2048b_1, pword ptr [rip + c]
P_256B_VADD R_0_R2048b_0, R_0_R2048b_1, R_0_R2048b_0
P_256B_STORE_DWORD pword ptr [rip + a], R_0_R2048b_0
I added the following lines in X86MCInstLower.cpp;
unsigned NewOpc;
switch (OutMI.getOpcode())
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Hello,
i want to work with these types v32f32, v32f64.... in llvm which are
undefined in the backend?
But v32i32, v32i64 are already defined so i am able to use these.
but for other types such as v32f32, v32f64 although i have defined them
appropriately in all the files like machinevaluetype.h, valuetypes.cpp
etc. i have checked it many times but still getting the following error
when build in
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Thank you so much. it run fine.
Can you please resolve following issue;
I now have support for v2048i32
but my backend supports v64i32
so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the
only difference between 2 is if its orginally v2048i32 i want my registers
assignment from REG_A set. if its v64i32 originally, then i want registers
from set REG_B.
How to accomplish
2017 Jul 12
2
Using new types v32f32, v32f64 in llvm backend not possible
I would be very grateful if you specify whether there is some way to
allocate registers (different order) / from different register sets to the
same instruction based on the vector width/ no of iterations.
I have tried several alternatives but could not succeed.
Also I have asked this question many times but no one responds.
Is there something wrong with this??
Kindly guide me.
Thank You
On
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I wanted to inform that I fixed the bug from the previous email.
The main reason for the bug was that I thought that the SDNode masked_gather is
returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult
to follow, error: "Assertion `New->getNumTypes() == 1").
masked_gather returns 2 values because:
// SDTypeProfile -
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I fixed the bug reported in the previous post on this thread
(<<llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&,
llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <=
MMO->getSize() && "Size mismatch!"' failed.>>)
The problem with this strange error reported comes from
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure: