similar to: LLVM back end for the research Connex SIMD processor

Hello. I started implementing a back end in LLVM (and I'm writing some hints I consider useful at https://sites.google.com/site/alexsusu/home/backend-llvm ). Unfortunately, I hit quite a few times very cryptic error messages when compiling with TableGen, which required a few good hours of debugging the TableGen program. The most cryptic error message was when compiling with

Hello, Anton, I'd like to add a small reply regarding this GSoC project that I would like to mentor and I discussed also with Andrei. A good part of our GSoC project is indeed related to this Connex back end that it's not yet part of the LLVM source repository - an important thing proposed in the project is that we plan to perform efficient realignment for this Connex vector

Hello, I am applying for Google Summer of Code with a project related to LLVM and Connex SIMD processor and I would appreciate some feedback on the proposal. The proposal can be found here: https://docs.google.com/document/d/1pBRbW8pU9GV8zWCJQrILhynNEBpGXJKtev1j7ekXfqs/edit?usp=sharing Thank you, Andrei Popa

Hello, i?ve Samba 4.7 with domain controller with 3 servers, 1 master (samba-ad) and two slaves (samba-slave1) and (samba-slave2). The problem is when create user account from "samba-ad? this account not sync to slave, but i create the account on "samba-slave1" or "samba-slave2? this is sync on all server. Samba version [???????.] root at samba-ad:~# samba -V Version

My domains dont see any traffic until you try to connect out from within the domain. Tried this several times and it was consistent. I have no firewall either. running each domain on different cpu probably doesn''t help, although Im no network expert. Here is some info. ================ [root@a root]# xm info system : Linux host : a.b.com release

Hello. I am writing a back end in which I combined the existing BPF LLVM back end with the Mips MSA vector extensions (from the Mips back end) I have encountered an error when compiling with llc: the instruction selector uses a vector register instead of a scalar register with type i64 . I have the following part of LLVM IR program: vector.body.preheader:

Hi Alex, We've only recently managed to get the core scalable vector IR type into the codebase (so it will be present in 9.0); that allows you to write IR with scalable vector types, but there's no backend able to generate code for it yet, and as you mention no support for stepvector (or vscale). Arm will start upstreaming those soon. -Graham > On 13 Jul 2019, at 14:32, Alex Susu via

Hello. I come back to this thread. But I want to ask a slightly different question. Is there a way to have LLVM IR language intrinsics that are given at construction time a string that is written at assembly generation time as it is? (so, basically having placeholders of strings in LLVM that remain untouched until the end, including code generation time.) More exactly, I would

Hello, I need some help with this problem that i have. I want to accept connection from 1 ip address to my linux box, but i cannot telnet the port 139. I added the rule in rules: ACCEPT net:xxx.xxx.xxx.xxx fw tcp 139 but still i cannot see this port from outside. >From inside the netowork everything is ok. Can someone tell me what i am doing worng? or what i need to do to be able to

Internet reports that I'm 1-of-many victims, failing to run linux on new/cheap laptops. Eg. quad-Atom; connex L1470. What is syslinux's recomended method to overcome <WinTel's UEFI lockout> using a USBbootStik ? Are wifi drivers: RTL8723BS for linux available yet ? ==TIA.

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return

Hi I've been trying to finally switch off our NT4 PDC over the last few months and transfer PDC duties to our Samba file server. Although I have no difficulty in getting the Samba box to authenticate users as the PDC, I have never been able to migrate the user's settings over. As far as the clients (NT4 and W2K) are concerned, users effectively start with a "clean slate" i.e.

Hi We've noticed that we get zero length files left behind on Samba shares after printing to a Samba printer, of the form NExx: (appears as NExx~yy) from Windows due to name mangling. This only occurs in specific circumstances: Client running NT4 (SP6a) and Printing file on a Samba share and Printing to a Samba printer and Running particular applications (e.g. Word and Acrobat, but not

I use rsync to mirror several servers. I run RH7.3 My rsyncd.conf file is: motd file = /etc/rsync.d/rsync.motd log file = /var/log/rsyncd.log pid file = /var/run/rsyncd.pid lock file = /var/run/rsync.lock hosts allow = 10.1.2.200 10.1.2.201 hosts deny = 0.0.0.0/0.0.0.0 use chroot = yes max connections = 3 #syslog facility = [website] path = /var/www/website comment = Connex Live WWW

Hello. For my back end for the Connex SIMD research processor I want to implement conditional blocks (I guess the better term is predicated blocks). Predicated blocks are bordered by two instructions WHEREEQ (or WHERELT, etc) and ENDWHERE. For example, the following code executes the instructions inside the WHERE block only for the lanes where R0 == R1: EQ R0, R1;

I had a phone conversation yesterday with Graham, Francesco, and Kristof. There is one more reason to go with the native type change: ARM has already written the code with the SV types, and they have patches ready to be reviewed and integrated in LLVM. As I don't want to stand in the way of getting SVE in LLVM as soon as possible, I will also support the integration of the existing patches

Hello. In my TableGen back end description I need to use more than 32 (e.g., 128, 1024, etc) subregisters per register for my research SIMD processor. I have used so far with success 32 subregisters. However, when using 128 subregisters when I now give the command: llvm-tblgen -gen-register-info Connex.td I get an error message "error:Ran out of lanemask bits to

Hi, I'm using voipbuster at work, and I've got 2 questions: 1) Is it possible to send faxes using voipbuster connex? 2) Is it possible to cut off or cover the voice that say the charge per minute?(I've payed the '5' euro, and from that moment I've got it!). Of course I understand that is to let me know how much I'm going to spend, but I do not like it, expecially when

Hi, I vaguely remember hitting something like this when I was implementing MSA. IIRC, there was an optimization (in DAGCombine or somewhere around there) that was folding CopyToReg instructions into the load without checking whether the new register class was acceptable. I remember adding a target hook to limit this optimization based on the EVT's involved but I'm not sure if that's

Hello. I've tried to add some simple arithmetic vector operations to the BPF backend available in the LLVM repo. Because I added in BPFRegisterInfo.td another RegisterClass (taken from the Mips backend): def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128, (sequence "W%u", 0, 31)>; in order to support vector for example, ADD