Displaying 20 results from an estimated 1000 matches similar to: "load with alignment of 1 crashes from being unaligned"
2017 Jun 19
2
LLVM behavior different depending on function symbol name
On Mon, Jun 19, 2017 at 12:06 PM, Mehdi AMINI <joker.eph at gmail.com> wrote:
> Hi,
>
> 2017-06-19 8:45 GMT-07:00 Andrew Kelley via llvm-dev <
> llvm-dev at lists.llvm.org>:
>
>> Greetings,
>>
>> I have a Zig implementation of ceil which is emitted into LLVM IR like
>> this:
>>
>> ; Function Attrs: nobuiltin nounwind
>> define
2017 Sep 16
2
assertion triggered since update to llvm 5
When zig updated to llvm 5 we started hitting this assertion:
zig:
/home/andy/downloads/llvm-project/llvm/include/llvm/Support/Casting.h:106:
static bool llvm::isa_impl_cl<To, const From*>::doit(const From*) [with To
= llvm::Instruction; From = llvm::Value]: Assertion `Val && "isa<> used on
a null pointer"' failed.
I wonder if however this was caused by an
2017 Sep 17
2
assertion triggered since update to llvm 5
Can you please open a bug on bugzilla and attach the ir testcase? Your fix
doesn't look right (just hiding the assertion failure)
On Sep 17, 2017 10:45 AM, "Andrew Kelley via llvm-dev" <
llvm-dev at lists.llvm.org> wrote:
> What do you think about this patch?
>
> --- a/llvm/lib/Transforms/Scalar/NewGVN.cpp
> +++ b/llvm/lib/Transforms/Scalar/NewGVN.cpp
> @@
2017 Sep 17
4
assertion triggered since update to llvm 5
So, 90% of the time I've seen this, it was memory corruption, usually use
after free. I know I fixed one after 5.0 branched.
You should compile with address sanitizer enabled, and I suspect you will
find the issue quicky.
If not, we really need ir that reproduces it.
On Sun, Sep 17, 2017, 12:27 PM Andrew Kelley via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> I think I forgot to
2017 Jun 19
2
LLVM behavior different depending on function symbol name
using `opt --print-after-all -O3` I see that EarlyCSE is interpreting the
call to `ceil` and constant fold:
*** IR Dump After Early CSE ***
; Function Attrs: nobuiltin nounwind
define i1 @do_test() #2 {
Entry:
%0 = call fastcc float @ceil(float 0.000000e+00) #6
%1 = call fastcc float @ceil32(float 0.000000e+00) #6
%2 = fcmp fast oeq float 0.000000e+00, %1
ret i1 %2
}
So just running `opt
2017 Jun 19
4
LLVM behavior different depending on function symbol name
Greetings,
I have a Zig implementation of ceil which is emitted into LLVM IR like this:
; Function Attrs: nobuiltin nounwind
define internal fastcc float @ceil(float) unnamed_addr #3 !dbg !644 {
Entry:
%x = alloca float, align 4
store float %0, float* %x
call void @llvm.dbg.declare(metadata float* %x, metadata !649, metadata
!494), !dbg !651
%1 = load float, float* %x, !dbg !652
%2 =
2017 Sep 17
2
assertion triggered since update to llvm 5
Dump the IR before newgvn and run through opt -newgvn. It should crash. I'm
not familiar with your frontend but you might want to use -mllvm
-opt-bisect-limit.
On Sep 17, 2017 1:06 PM, "Andrew Kelley" <superjoe30 at gmail.com> wrote:
Valgrind is strictly better than address sanitizer, is that right? It runs
valgrind-clean:
[nix-shell:~/dev/zig/build-llvm5-debug]$ valgrind
2017 Nov 15
2
workaround for debug info bug?
I just reported this bug:
https://bugs.llvm.org/show_bug.cgi?id=35314
This very simple IR is causing infinite recursion
in llvm::DwarfUnit::getOrCreateTypeDIE in llvm 5.0.0.
Is there a workaround? Is anyone willing to save me a recompile and check
if this is fixed in 5.0.1 or trunk?
`clang -c test.ll` repros the issue.
; ModuleID = 'test'
source_filename = "test"
target
2019 Jan 19
2
What does "preds" mean in a .ll file?
Hi,
I see things like this. What does it mean? Is it documented somewhere? Thanks.
; preds = %for.body
https://llvm.org/docs/LangRef.html
; <label>:91: ; preds = %88
%92 = load i8**, i8*** @glob_complete_word.matches, align 8, !dbg !99798
%93 = load i32, i32* @glob_complete_word.ind, align 4, !dbg !99799
%94 = sext i32 %93 to i64, !dbg !99798
2018 Jul 25
2
A question to the DWARF experts on symbol indirection
> -----Original Message-----
> From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Tim
> Northover via llvm-dev
> Sent: Wednesday, July 25, 2018 3:07 AM
> To: Nat!
> Cc: LLVM Developers Mailing List
> Subject: Re: [llvm-dev] A question to the DWARF experts on symbol
> indirection
>
> Hi Nat!,
>
> On Wed, 25 Jul 2018 at 01:21, Nat! via
2016 Apr 30
2
Debug info scope of explicit casting type does not seem correct
Hi,
I am wondering if this behavior of creating debug info is correct.
A type in compile unit entry is pointing to a type under subprogram entry?!
This is the root cause of https://llvm.org/bugs/show_bug.cgi?id=27579
0x0000000b: DW_TAG_compile_unit [1] *
0x00000026: DW_TAG_pointer_type [2]
DW_AT_type [DW_FORM_ref4] (cu + 0x002c => {0x0000002c})
2008 Nov 26
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
> I disagree. This should be handled by the type legalization
> infrastructure.
huh...
As far as I know, the type legalization is in the SelectionDAG phase,
and it is also in the backend. Am I right? or I miss something.
> there is currently no support for anything like f32 -> f24
You say "there is currently no support for anything like f32 -> f24",
does it means I can
2008 Nov 26
1
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
I think Duncan and I disagree. Generally I would defer to anybody else
on this list: my experience is backend Target only, with very little
poking around the internals. I'm usually asking, not answering,
questions here: the 24 bit floats reminded me of the "good old days"
at ATI.
That said, I think you could make f32/i32 work for your purposes -
given the limited types
2008 Nov 25
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Hi,
> I am not sure how legalizer and friends deal with i24 / f24 as legal
> types.
the type legalizer currently assumes that all legal integer types
have a power-of-two number of bits. I don't see any obstacles to
making it more general though. First off, i24 would need to be
added to the list of simple value types. Then the integer promotion
and expansion logic would need to be
2014 Oct 21
2
[LLVMdev] Question regarding getElementPtr/Addressing modes in backend
Hi,
I am writing a backend and having issues with properly lowering the result
of getElementPtr ( specifically the add node that it generates).
If we take this IR:
%struct.rectangle = type { i24, i24 }
; Function Attrs: nounwind readonly
define i24 @area(%struct.rectangle* nocapture readonly %r) #0 {
entry:
%width = getelementptr inbounds %struct.rectangle* %r, i16 0, i32 0
%0 = load i24*
2008 Nov 26
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
On Wednesday 26 November 2008 09:31:26 Wei wrote:
> O...k... I try to make some conclusions:
>
> 1) The conversion from f32 to f24 or i32 to i24 should be written in
> the backend.
I disagree. This should be handled by the type legalization
infrastructure. After all, that's what it is for! However
there is currently no support for anything like f32 -> f24.
On the other
2016 May 07
2
Debug info scope of explicit casting type does not seem correct
Hi David,
OK, I got that DIE in Compile Unit scope may point to a DIE in subprogram scope.
But how about that we are emitting a subprogram entry that has no attributes?
0x0000002b: DW_TAG_subprogram [3] *
0x0000002c: DW_TAG_typedef [4]
DW_AT_type [DW_FORM_ref4] (cu + 0x0040 => {0x00000040})
DW_AT_name [DW_FORM_strp] (
2008 Nov 26
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
O...k... I try to make some conclusions:
1) The conversion from f32 to f24 or i32 to i24 should be written in
the backend.
Because we should not put any hardware dependent behaviors in the
frontend. If we may change our H/W platform to another one which
supports f32, i32 natively, we will only need to change the backend
codes.
For example:
The backend approach means that integer division is a
2014 Oct 23
2
[LLVMdev] Question regarding getElementPtr/Addressing modes in backend
Hi Steve,
Thanks for the tip regarding MIOperandInfo, I didn't think of that part of
the tablegen description.
Sadly, I did actually mean: r1 = *(i0 += m0).
So increment i0 by m0. Read memory the memory location "pointed" to by i0.
Store in r1. Sadly I am not too familiar with compiler terminology, so I
don't know if there is a proper term for such a load.
On Thu, Oct 23,
2008 Nov 24
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
On Nov 22, 2008, at 7:48 AM, Wei wrote:
> Do you mean MVT::getIntegerVT? Because I can not find
> getExtendedIntegerVT in the llvm source codes.
> I am excited seeing this function, however I have the following more
> questions.
See ValueTypes.h and ValueTypes.cpp. Also this example:
@str = internal constant [4 x i8] c"%d\0A\00"
define void @foo2(i24 %a, i24 %b) nounwind