similar to: TableGen questions.

Hello all, I have two Tablegen questions in the context of an unconventional architecture. The pertinent details: the architecture has multiple register files that are selected via a bit in the instruction. One of the register files is a traditional one. The other is unconventional in that all source and dest registers are both read from and written to by the instructions. So add special0,

Hello, I am having some trouble matching patterns in targetinstructioninfo.td file with the CodeGen expectation. Could anybody please help? Here is the example: I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc I define the instruction TargetInstruction.td as follows: class MyInst <opcode

Colleagues, one of my servers had to be rebooted uncleanly and then I have backgrounded fsck locked for more than an our in snaplk: 742 root 1 -4 4 1320K 688K snaplk 0:02 0.00% fsck_ufs File system in question is 200G gmirror on SATA. Usually making a snapshot (e.g., for making dumps) consumes 3-4 minutes for that fs, so it seems to me that filesystem is in a deadlock. Any

If you're one of the people who has cvsup'd to 4.8-stable since August 8th and you've since begun to experience panics on a previously stable system, please apply the attached patch and see if your previous stability has been restored. Please tell me your results. Thanks, Mike "Silby" Silbersack -------------- next part -------------- diff -u -r

Hello, The Xen community is working on a new virtualization mode (or maybe I should say an extension of HVM) to be able to run PV guests inside HVM containers without requiring a device-model (Qemu). One of the advantages of this new virtualization mode is that now it is much more easier to port guests to run under it (as compared to pure PV guests). Given that FreeBSD already supports