similar to: [iovisor-dev] [PATCH RFC 0/4] Initial 32-bit eBPF encoding support

On Sat, Sep 23, 2017 at 1:41 AM, Jakub Kicinski via iovisor-dev <iovisor-dev at lists.iovisor.org> wrote: > On Fri, 22 Sep 2017 22:03:47 -0700, Yonghong Song wrote: >> On 9/22/17 9:24 AM, Jakub Kicinski wrote: >> > On Thu, 21 Sep 2017 11:56:55 -0700, Alexei Starovoitov wrote: >> >> On Wed, Sep 20, 2017 at 12:20:40AM +0100, Jiong Wang via iovisor-dev wrote:

On Wed, Sep 20, 2017 at 12:20:40AM +0100, Jiong Wang via iovisor-dev wrote: > On 18/09/2017 22:29, Daniel Borkmann wrote: > > On 09/18/2017 10:47 PM, Jiong Wang wrote: > > > Hi, > > > > > >    Currently, LLVM eBPF backend always generate code in 64-bit mode, > > > this may > > > cause troubles when JITing to 32-bit targets. > > >

On 09/18/2017 10:47 PM, Jiong Wang wrote: > Hi, > > Currently, LLVM eBPF backend always generate code in 64-bit mode, this may > cause troubles when JITing to 32-bit targets. > > For example, it is quite common for XDP eBPF program to access some packet > fields through base + offset that the default eBPF will generate BPF_ALU64 for > the address formation, later when

On 06/16/2016 06:57 PM, Richard Henderson via iovisor-dev wrote: > On 06/15/2016 10:14 PM, Alexei Starovoitov wrote: >> On Wed, Jun 15, 2016 at 2:37 PM, Richard Henderson via iovisor-dev >> <iovisor-dev at lists.iovisor.org> wrote: >>> This same value for EM_BPF is being propagated to glibc, >>> elfutils, and binutils. >> >> great! >> Can

Hi, Jiong, Thanks for the patch! It is a great start to support 32bit register in BPF. In the past, I have studied a little bit to see whether 32bit register support may reduce the number of unnecessary shifts on x86_64 and improve the performance. Looking through a few bpf programs and it looks like the opportunity is not great, but still nice to have if we have this capability. As you

On Wed, Jun 15, 2016 at 2:37 PM, Richard Henderson via iovisor-dev <iovisor-dev at lists.iovisor.org> wrote: > This same value for EM_BPF is being propagated to glibc, > elfutils, and binutils. great! Can you share the link to glibc and the other patches? > diff --git a/include/llvm/Support/ELF.h b/include/llvm/Support/ELF.h > index 352fd8a..fb8ff71 100644 > ---

Hi all, I'm working on a target whose registers have equal-sized subregisters and all of those subregisters can be named (or the other way round: registers can be grouped into super registers). So for instance we've got 16 registers W (as in wide) W0..W15 and 32 registers N (as in narrow) N0..N31. This way, W0 is made by grouping N0 and N1, W1 is N2 and N3, W2 is N4 and N5, ..., W15 is

Hi, I'm stuck trying to fix a variety of problems that occur with undef subregisters when the register coalescer eliminates identity copies. The fundamental problem is complexity from the fact that undef values are a special case since they don't have an associated VNInfo/Segment unless the value is used across blocks. For example, in this case, %0 has 2 subregisters sub0 and sub1:

Hi, Jiong, The new patch looks good. I did some basic testing on net-next:samples/bpf and net-next:tools/testing/selftests/bpf and it works fine. All existing llvm unit tests are not impacted as well as expected. I have applied the patch to the trunk. Besides your other work to support 32bit abi, it would be interesting to see how new 32bit register can be used in 64bit architecture which may

Hi All, I'd like to propose to upgrade BPF backend to first class citizen. Current status of it: - used with linux kernel on x64, arm64, s390 architectures - projects that use it: perf, tc, ovs - there are few front-ends in the works: . one is translating custom language to C and then using clang/llvm . another is generating llvm IR directly . yet another is using clang rewriter to

I've been working on patches to improve subregister liveness tracking on llvm and I wanted to inform the llvm community about the overal design/motivation for them. I will send the patches to llvm-commits later today. Greetings Matthias Braun Subregisters in llvm ==================== Some targets can access registers in different ways resulting in wider or narrower accesses. For

What I didn't mention in r192119 is that mthi/lo clobbers the other sub-register only if the contents of hi and lo are produced by mult or other arithmetic instructions (div, madd, etc.) It doesn't have this side-effect if it is produced by another mthi/lo. So I don't think making mthi/lo clobber the other half would work. For example, this is an illegal sequence of instructions,

Currently it will always spill / restore the whole vreg but only spilling the parts that are actually live would be a nice addition in the future. Looking at r192119': if "mtlo" writes to $LO and sets $HI to an unpredictable value, then it should just have an additional (dead) def operand for $hi, shouldn't it? Greetings Matthias Am 10/8/13, 11:03 AM, schrieb Akira

ComRades: I am geeting the error message Error in ldots[[which(MET)]] : attempt to select less than one element when I try to fit the geostatistical model with the likfit() function of geoR. I have tried with old data for which likfit() successfully maximised the likelihood in previous versions of geoR, and yet the current version fails. I have tried in Windows Vista and Windows XP (I haven't

I have a bit of an issue with rsync. I am using to keep directories in sync via another server for backup. Here is the server config [w1] path = /w1 comment = w1 web dir [w2] path = /w2 comment = w2 web dir Now on the client i run this command rsync -avv --delete --force domain.com::w1/ /w1/ It will NOT delete anything that is no on the server anymore.. for example on the server/client there

Hi, I would like to create wireframe plots conditional on 2 variables and use different limits for the 3-axes in each plot. I thought I could do this with subscripts and the panel.wireframe but I haven't been successful. I am getting this error "...multiple actual arguments..." so I definitely don't have something set up correctly. Listed below is the code to generate the

Hello. In my TableGen back end description I need to use more than 32 (e.g., 128, 1024, etc) subregisters per register for my research SIMD processor. I have used so far with success 32 subregisters. However, when using 128 subregisters when I now give the command: llvm-tblgen -gen-register-info Connex.td I get an error message "error:Ran out of lanemask bits to

Jim has been exceedingly patient (and may well continue to be so), but this smells like "failure to launch". At what point will you start showing your (failed) attempts at solving your own problems so we can help you work on your specific weaknesses and become self-sufficient? -- Sent from my phone. Please excuse my brevity. On February 25, 2018 7:55:55 AM PST, Val <valkremk at

On Mon, Mar 06, 2023 at 05:58:30PM +0100, Roberto Sassu wrote: > If there is no hook registering to inode_init_security, theoretically > the LSM infrastructure should return -EOPNOTSUPP, which causes ocfs2 to > set si->enable to zero, and not execute the line that causes the kernel > to panic. > > The problem would arise if somehow the LSM infrastructure returns zero, >

Woud it be reasonable to assert that TargetRegisterInfo::isSubRegister() is a transitive relation? In other words, if A is a subregister of B and B is a subregister of C then A is a subregister of C. With this assumption, we could teach TableGen to sort registers topologically such that all the subregisters of R are numbered R+1, R+2, ... This produces better locality of reference and allows