similar to: Conversion of const llvm::MCExpr * to string

Displaying 20 results from an estimated 500 matches similar to: "Conversion of const llvm::MCExpr * to string"

2011 Oct 18
0
[LLVMdev] Question about MCExpr and subclasses
That just means the ELF writer doesn't know yet how to deal with the target-specific data. It needs taught how to map them onto relocations and such. Do you really need to subclass MCTargetExpr? That's ordinarily only for operands that aren't representable via the normal MC stuff (for example, the ARM movw/movt relocations). You should be able represent normal symbol operands w/o
2011 Oct 18
4
[LLVMdev] Question about MCExpr and subclasses
I have a question about MCExpr and its subclasses defined in MCExpr.h. I am trying to get Mips' direct object emission working. Line 283 of MCElfStreamer.cpp reads like this: 00283 case MCExpr::Target: llvm_unreachable("Can't handle target exprs yet!"); Does this mean that if I use a subclass of MCTargetExpr to lower MachineOperands to MCOperands, it won't work?
2011 Oct 19
0
[LLVMdev] Question about MCExpr and subclasses
HI Akira, Please include the mailing list on replies. Using an MCExpr is the right way to build up things like symbol+offset. ARM has examples for that, as well, which may prove useful. For printing, the target libraries can do that however they want, including using the generic print method for expressions (or not). Often, the generic printing is sufficient, but not always. You can register a
2016 Jun 13
2
Is addrspace info available during instruction scheduling?
We'd like to be able to vary the latency of our load instructions based on what address space is being loaded from. I was thinking I could do this by overriding getOperandLatency in our target, but I'm wondering if the addrspace info is available when instructions are scheduled? For example, I have this in our llvm IR: %0 = load i32 addrspace(4)* @answer, align 4 store i32 %0, i32*
2010 Jul 14
2
[LLVMdev] Win32 COFF Support - Patch 3
On Sun, Jul 11, 2010 at 6:10 PM, Chris Lattner <clattner at apple.com> wrote: > This probably needs to be slightly tweaked to work with mainline.  I don't see anything objectionable, but I think Daniel needs to review this one. Updated patch to work with mainline. http://github.com/Bigcheese/llvm-mirror/commit/d19a4c82c18afc4830c09b70f02d162292231c94 - Michael Spencer
2015 Dec 14
3
Getting TargetLowering in AsmPrinter / Lowering constant addrspacecast
Hi, I'd like to add support for addrspacecast in initializers of global variables, at least for the trivial case. The trivial case is if TargetLowering::isNoopAddrSpaceCast(SrcAS, DestAS) returns true. In this case the MCExpr for the addrspacecast is the MCExpr of its first operand. It seems hard to obtain an instance of TargetLowering in AsmPrinter::lowerConstant(). Other methods in
2010 Oct 21
5
[LLVMdev] [llvm-commits] Fwd: Proof of concept patch for unifying the .s/ELF emission of .ARM.attributes
> Also what is the preferred method for MC way of setting out subsection > sizes after the fact? I am guessing I need to use an MCFixup? > How do I get an MCExpr to evaluate a method for the subsection size? > Is there an equivalent use in the places using MCFixup? > Do I need to add a new subclass to MCExpr for doing this? > > JimG, can you please comment on the MachO
2013 Nov 12
2
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi David, Thanks for your efforts here. I have a few comments on your patch, although I realise it's still a work in progress. +class ConstantPool { + MCSymbol *Label; + typedef std::vector<const MCExpr*> EntryVecTy; Use a SmallVector here? + MCSymbol *getLabel() {return Label;} + size_t getNumEntries() {return Entries.size();} + const MCExpr *getEntry(size_t Num) {return
2010 Oct 21
3
[LLVMdev] [llvm-commits] Fwd: Proof of concept patch for unifying the .s/ELF emission of .ARM.attributes
> Hmm, I wish we had this discussion way earlier.. > > How would I emit things in different subsections? I can do a high > level switch to .ARM.attributes, and if I were emitting one blob from > begin to end, using the higher level interface would be preferable, > but it contains additional subsections - which are naturally > represented by MCDataFragments - Is there an MC
2010 Oct 21
0
[LLVMdev] [llvm-commits] Fwd: Proof of concept patch for unifying the .s/ELF emission of .ARM.attributes
On Thu, Oct 21, 2010 at 7:50 AM, Rafael Espíndola <rafael.espindola at gmail.com> wrote: >> Hmm, I wish we had this discussion way earlier.. >> >> How would I emit things in different subsections? I can do a high >> level switch to .ARM.attributes, and if I were emitting one blob from >> begin to end, using the higher level interface would be preferable,
2014 Apr 08
2
[LLVMdev] 3.4.1 Release Plans
On Tue, Apr 08, 2014 at 04:08:13PM +0400, Robert Khasanov wrote: > Hi Reid, > > Would you approve your patches r203146 and r202774 to be backported to > 3.4.1? They fix stability issues in x86 asm. > Hi Robert, I was able to merge r203146, but it used a c++11 feature: std::string::back() which I replaced with std::string::at(std::string::size() - 1). r202774 was not merged,
2013 Oct 10
2
[LLVMdev] [PATCH] R600/SI: Embed disassembly in ELF object
Hi, This patch adds R600/SI disassembly text to compiled object files, when a code dump is requested, to assist debugging in Mesa clients. Here's an example of the output in a Mesa client with a corresponding patch and RADEON_DUMP_SHADERS set: Shader Disassembly: S_WQM_B64 EXEC, EXEC ; BEFE0A7E S_MOV_B32 M0, SGPR6 ; BEFC0306
2012 Oct 16
2
[LLVMdev] R_ARM_ABS32 disassembly with integrated-as
Attached is an example of how to reproduce the issue. It uses a C file that happens to has a bunch of switch statements which are encoded as jump tables, giving us data-in-code. Usage: To build object files with clang via the -integrated-as versus via GCC: $ export NDK_DIR=<my_ndk_dir> $ export LLVM_DIR=<my_llvm_bin_dir> $ make To test that the generated objects contain the same
2013 Nov 12
0
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
Hi Amara, Thanks for your suggestions. I have made the changes you suggested and added a new test to check that we print an error when parsing a non-ldr mnemonic with an operand containing `=`. The updated patch is attached. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > -----Original Message----- > From: Amara Emerson
2013 Nov 11
0
[LLVMdev] Implementing the ldr pseudo instruction in ARM integrated assembler
I have attached an initial patch that implements the ldr pseudo. It still needs some clean up and more tests, but I would like some feedback on the approach I used and if there are any objections to implementing it this way. Here is my approach: Add a finishParse() callback to the target asm parser This callback is invoked when the parse has finished successfully. It will be used to write out
2010 Jul 27
3
[LLVMdev] Win32 COFF Support patch 5 (the final patch in the saga!)
Daniel somehow replied to one of my previous commits on llvm-commits instead of this thread. On Mon, Jul 26, 2010 at 12:41 AM, Daniel Dunbar <daniel at zuster.org> wrote: > Hi Michael, > > Two minor notes: > -- >> diff --git a/lib/Target/X86/X86AsmBackend.cpp b/lib/Target/X86/X86AsmBackend.cpp >> index 2cf65c1..02ac2be 100644 >> ---
2014 Feb 04
3
[LLVMdev] emitting function stub for mips16 floating point patch
On 02/04/2014 09:58 AM, Rafael Espíndola wrote: >> .align > > So yes, EmitValueToAlignment. > > Cheers, > Rafael > One more::: OutStreamer.EmitRawText("\t.size __call_stub_fp_" + Twine(Symbol) + ", .-__call_stub_fp_" + Twine(Symbol)); You have to make an expression???? i.e. .size __call_stub_fp___floatdidf,
2012 Jan 19
2
[LLVMdev] [PATCH] TLS support for Windows 32+64bit
Hi! I added 2 more tests and also refined an assert statement. Applies cleanly to r148473 now. Are there more comments on the code? Thank you!! Regards Kai On 01.01.2012 22:01, Eli Friedman wrote: > On Sun, Jan 1, 2012 at 10:44 AM, Kai<kai at redstar.de> wrote: >> Happy new year to all! >> >> The attached patch adds TLS support for x86_64-pc-win32 and x86-pc-win32.
2015 Aug 02
2
[LLVMdev] Unable to generate obj file using llc for bpf
Dear there, I wasn't able to generate obj file for bpf using llc: llc -march bpf -filetype=obj foo.bc Anyone knows what is the missing part in their backend? I want to make it work for my project. Thanks, Xiaochu -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150802/e0b55467/attachment.html>
2011 Apr 26
2
[LLVMdev] Symbol folding with MC
Hello, I have some questions regarding folding operations with symbols during the instruction print stage with MC. At the moment I'm working with global symbols but i guess that other symbol types should be equivalent. My first question is how can i negate the address of a symbol? Consider this piece of code: char g_var[80]; char foo(int a) { return g_var[a]; } this gets compiles into