Displaying 20 results from an estimated 30000 matches similar to: "[IR question] Switching on pointers"
2017 May 16
2
[IR question] Switching on pointers
Thanks everyone for your answers.
Mats, my goal is do an alternate implementation of the subtyping test
in the Pony compiler. I'll try to keep the explanation short to avoid
cluttering the mail with irrelevant information.
Every object in Pony has a type descriptor, which is used in the
subtyping test to determine the real type of an object. The current
algorithm is suboptimal and
2011 Nov 02
1
[LLVMdev] [LLVMDev]: UNREACHABLE executed!
Hi, guys!
I write a virtual machine which uses LLVM as back-end code generator. The
following function code causes strange "UNREACHABLE executed!" error:
define void @p1(%1*) {
%2 = call i8* @llvm.stacksave()
%3 = alloca %0
%4 = getelementptr %0* %3, i64 1
%5 = ptrtoint %0* %3 to i64
%6 = ptrtoint %0* %4 to i64
%7 = sub i64 %6, %5
%8 = bitcast %0* %3 to i8*
call void
2015 Mar 25
3
[LLVMdev] Optimization puzzle...
Here's a version that doesn't try to do block deletion on it's own. If you
use -adce then -simplifycfg, you get what you want.
It passes all tests except one, which is that we delete an invoke of a pure
function, IE Transforms/ADCE/dce_pure_invoke.ll -
I'm not sure why that's bad.
The reason we delete it is because it returns false to
I.mayHaveSideEffects(), and in particular,
2007 Apr 02
1
RODBC, sqlQuery with NA:s
Hi R-users,
I'm trying to retrieve data from MS SQL database with RODBC's
sqlQuery-function:
temp <- sqlQuery(channel,"select *, (select text from table1 where
koodi='paa' and koodi2=paa) as tempor from table2")
str(temp)
…
$ var0 : num NA NA 1.6 NA NA 1.4 NA 1 NA NA ...
$ var1 : Factor w/ 45 levels "
2017 Dec 19
4
A code layout related side-effect introduced by rL318299
Hi,
Recently 10% performance regression on an important benchmark showed up
after we integrated https://reviews.llvm.org/rL318299. The analysis showed
that rL318299 triggered loop rotation on an multi exits loop, and the loop
rotation introduced code layout issue. The performance regression is a
side-effect of rL318299. I got two testcases a.ll and b.ll attached to
illustrate the problem. a.ll
2017 Dec 19
2
A code layout related side-effect introduced by rL318299
On Mon, Dec 18, 2017 at 5:46 PM Xinliang David Li <davidxl at google.com>
wrote:
> The introduction of cleanup.cond block in b.ll without loop-rotation
> already makes the layout worse than a.ll.
>
>
> Without introducing cleanup.cond block, the layout out is
>
> entry->while.cond -> while.body->ret
>
> All the arrows are hot fall through edges which is
2018 Jun 27
2
can debug info for coroutines be improved?
I'm going to show the same function, first normally, and then as a
coroutine, and show how gdb can see the variable when it's a normal
function, but not when it's a coroutine. I'd like to understand if this can
be improved.
I'm trying to debug a real world problem, but the lack of debug info on
variables in coroutines is making it difficult. Should I file a bug? Is
this a
2017 Jun 17
5
LoopVectorize fails to vectorize loops with induction variables with PtrToInt/IntToPtr conversions
Hello all,
There is a missing vectorization opportunity issue with clang 4.0 with
the file attached.
Indeed, when compiled with -O2, the "op_distance" function get
vectorized, but not the "op" one.
For information, this test case has been reduced from a file generated
by the Pythran compiler (https://github.com/serge-sans-paille/pythran).
If we take a look at the generated
2017 Apr 24
3
Debugging UNREACHABLE "Couldn't join subrange" in RegisterCoalescer (out-of-tree backend)
Hello,
I have a minimal testcase which crashes RegisterCoalescer in my out-of-tree target. It only crashes in Debug builds of llc---not in Release builds. Also, interesting to note that the x86 backend lowers this same testcase successfully. I did a quick search of bugs.llvm.org and found no matches.
This implies that the problem is in my backend and/or how my backend interacts with
2010 Jul 14
2
[LLVMdev] Figuring out the parameters of the Call Instruction
Hi,
I am trying to figure out how to read arguments of a call instruction.
I had few questions based on that
I have the following C Code
1 #include <stdio.h>
2
3 struct my_struct
4 {
5 int a;
6 int b;
7 };
8
9 struct my_struct abc;
10 void p_ptr ( unsigned long j)
11 {
12 printf ( "%lx \n", j );
13 }
14
15 void struct_ptr ( struct my_struct *
2014 Sep 05
4
[LLVMdev] [cfe-dev] Address sanitizer regression test failures for PPC64 targets
Note that I've set the SA_NODEFER flag for the SEGV handler in the
ASan runtime only a couple of days ago.
Not sure that could've affected this test though; without that flag
the second SEGV would've simply crashed the program. But you can try
removing the flag from
compiler-rt/trunk/lib/sanitizer_common/sanitizer_posix_libcdep.cc and
see if that makes any difference.
HTH,
Alex
On
2014 Dec 26
3
[LLVMdev] Correct usage of `llvm.assume` for loop vectorization alignment?
Using LLVM ToT and Hal's helpful slide deck [1], I've been trying to use
`llvm.assume` to communicate pointer alignment guarantees to vector load
and store instructions. For example, in [2] %5 and %9 are guaranteed to be
32-byte aligned. However, if I run this IR through `opt -O3 -datalayout
-S`, the vectorized loads and stores are still 1-byte aligned [3]. What's
going wrong? Do I
2016 Feb 09
3
[GVN] same sequence of instructions in if and else branch
Hello,
I found that GVN doesn't promote identical sequence of instructions in if and else branch to their common predecessors. For example, for the following code snippet
pred:
…
br i1 %cmp, label %if, label %else
if:
%incdec.ptr.1 = getelementptr inbounds i8, i8* %ptr, i64 1
%cast1 = ptrtoint i8* %incdec.ptr.1 to i64
…
else:
%incdec.ptr.2 = getelementptr inbounds i8, i8* %ptr,
2017 Sep 16
2
assertion triggered since update to llvm 5
When zig updated to llvm 5 we started hitting this assertion:
zig:
/home/andy/downloads/llvm-project/llvm/include/llvm/Support/Casting.h:106:
static bool llvm::isa_impl_cl<To, const From*>::doit(const From*) [with To
= llvm::Instruction; From = llvm::Value]: Assertion `Val && "isa<> used on
a null pointer"' failed.
I wonder if however this was caused by an
2020 Jan 13
2
Incorrect code generation when using -fprofile-generate on code which contains exception handling (Windows target)
I think this is the same underlying issue as https://bugs.llvm.org/show_bug.cgi?id=40320. CCing Reid, who's had a bunch of thoughts on this in the past.
On 1/11/20, 10:25 AM, "llvm-dev on behalf of Chrulski, Christopher M via llvm-dev" <llvm-dev-bounces at lists.llvm.org on behalf of llvm-dev at lists.llvm.org> wrote:
Hi,
I've run into a bug with the LLVM
2017 Sep 17
2
assertion triggered since update to llvm 5
Can you please open a bug on bugzilla and attach the ir testcase? Your fix
doesn't look right (just hiding the assertion failure)
On Sep 17, 2017 10:45 AM, "Andrew Kelley via llvm-dev" <
llvm-dev at lists.llvm.org> wrote:
> What do you think about this patch?
>
> --- a/llvm/lib/Transforms/Scalar/NewGVN.cpp
> +++ b/llvm/lib/Transforms/Scalar/NewGVN.cpp
> @@
2010 Jul 15
0
[LLVMdev] Figuring out the parameters of the Call Instruction
Hi Shankha,
> 24 p_ptr ((unsigned long)&abc);
> call void @p_ptr(i64 ptrtoint (%struct.my_struct* @abc to i64))
> nounwind, !dbg !31
>
> Q.1 At line no 24 I try to read the address of global variable abc.
> The address is type casted
> from struct * to int * for which ptrtoint.
I guess you mean "is type casted from struct * to unsigned
2017 Sep 17
4
assertion triggered since update to llvm 5
So, 90% of the time I've seen this, it was memory corruption, usually use
after free. I know I fixed one after 5.0 branched.
You should compile with address sanitizer enabled, and I suspect you will
find the issue quicky.
If not, we really need ir that reproduces it.
On Sun, Sep 17, 2017, 12:27 PM Andrew Kelley via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> I think I forgot to
2015 Mar 25
2
[LLVMdev] Optimization puzzle...
Hi everyone,
I am wondering what¹s stopping the LLVM optimizer (opt -O3) from
eliminating the apparently useless « icmp sgt » instruction in the
following piece of LLVM IR.
> ; ModuleID = 'lambda-opt.bc'
> target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
> target triple = "x86_64-apple-macosx10.10.0"
>
> ; Function
2019 Sep 02
3
AVX2 codegen - question reg. FMA generation
Hello,
On the appended reasonably simple test case that has an fmul/fadd
sequence on <8 x float> vector types, I don't see the x86-64 code
generator (with cpu set to haswell or later types) turning it into an
AVX2 FMA instructions. Here's the snippet in the output it generates:
$ llc -O3 -mcpu=skylake
---------------------
.LBB0_2: # =>This Inner