similar to: Help with setting up ARM embedded clang + lld

Ok, thanks! I got it going that way. I'd still love to hear from anyone off list working on similar stuff. ~Scott On Sun, Apr 30, 2017, at 03:32 PM, Joerg Sonnenberger wrote: > On Sun, Apr 30, 2017 at 03:18:35PM -0700, Scott Shawcroft via llvm-dev > wrote: > > Hi all, > > I've been doing a ton of embedded work (bare metal ARM Cortex M0+ and > > M4, hopefully RISCV

On 2 May 2017 at 23:59, Rui Ueyama <ruiu at google.com> wrote: > That's interesting. Usually your code wouldn't be gc'ed because your entire > code is reachable from _start. Baremetal doesn't need a _start. > Does your program depend on the feature that, if no -e option is given, the > linker sets the beginning of the .text section to the entry point address?

Awesome! I got lld running but it GCed all my sections away. :-) I'll keep experimenting with it. ~Scott On Mon, May 1, 2017, at 07:11 AM, Renato Golin wrote: > On 30 April 2017 at 23:47, Scott Shawcroft via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > Ok, thanks! I got it going that way. I'd still love to hear from anyone > > off list working on similar

I am using llvm-project compiling risc-v programs. llvm-project version:dd8a2013dc1804be1b7d9cffacad2e984300bd22 Instructons to build LLVM+clang: ``` cmake -G Ninja -DCMAKE_INSTALL_PREFIX=/home/llvm/workspace/llvm/llvm-project/llvm_install -DCMAKE_BUILD_TYPE="Release" -DDEFAULT_SYSROOT="/home/llvm/workspace/riscv/riscv-tc-20200220/bin/riscv32-unknown-elf"

H all, I'm looking at generating PIC code for RISC-V in the context of Linux. Not sure if anyone is working on this already, any inputs are very welcome. I'm now looking at function calls which in the RISCV backend are represented via two pseudoinstructions RISCV::TAIL and RISCV::CALL. Currently those pseudos are lowered in MCCodeEmitter. They are expanded into AUIPC and JALR

I am linking a program to be loaded in an ARM Cortex-M0+ based microcontroller. In the linker script, I have a section allocated for the stack which roughly looks like the following. .stack : { . += __stack_size__; } > ram Using the linker in the gcc arm toolchain, arm-none-eabi-ld, this section is automatically set to type NOBITS, however, when linking with version 10.0.0 of ld.lld, the

I think it’s generally true that whenever branches can reliably be predicted branching is faster than a cmov that involves speculative execution, and I would guess that your assessment regarding looping on input values is probably correct. I believe the code that actually creates most of the transformation you’re interested in here is in SelectionDAGLegalize::ExpandNode() in LegalizeDAG.cpp. The

Alex, ping? There was a thread about moving Risc-V out of experimental but I think it didn't go anywhere? Separately, do the listed patches sound okay for merging? Thanks, Hans On Fri, Jan 25, 2019 at 4:40 PM Bruce Hoult <brucehoult at sifive.com> wrote: > > In https://llvm.org/svn/llvm-project/llvm/branches/release_80 I find > that RISCV is still in

Hi, I would like to start a new porting of GlobalIsel for RISCV. An initial patch about GlobalIsel infrastructure for RISCV was ready now: https://reviews.llvm.org/D65219 There is another porting patch https://reviews.llvm.org/D41653 posted by Leslie Zhai at the end of 2017. I have checked with Leslie about the status of this patch.He has stopped developing it since some questions need be

<div> </div><div><div><p>Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more.</p><p>This proposal is to add a <code>llvm.clmul</code> instruction. Or if that is contentious, <code>llvm.experimental.bitmanip.clmul</code> instruction.

Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructions or at least to find a way to

Hi Devs, since risc-v has a register $tp which is thread pointer. is it possible to have __builtin_thread_pointer for RISC-V? I am not sure what could be corresponding instructions? ./kamlesh

I am maintaining proprietary extensions to the RISCV backend for our custom application. I have defined intrinsics for many of the custom instructions. Against LLVM 7 this was working well. When I try to merge my changes into LLVM 10, I get: /home/dej/work/llvm_git/llvm-project/llvm/build/lib/Target/RISCV/RISCVGenGlobalISel.inc:11582:60: error: ‘idaho_mt_begin’ is not a member of

Hi, On Wed, Jul 12, 2017 at 2:21 AM, Rui Ueyama via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Thanks, Bruce. This is a very interesting optimization. > > lld doesn't currently have code to support that kind of code shrinking > optimization, but we can definitely add it. It seems that essentially we > need to iterate over all relocations while rewriting

On Tue, 21 Jan 2020 at 01:14, Chris Lattner <clattner at nondot.org> wrote: > > On Jan 16, 2020, at 10:01 AM, Alex Bradbury via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I believe code should be committed to LLVM when it is of sufficient > > quality, when it can be shown to benefit the LLVM user or developer > > communities, and when there is someone

I tried to build LLVM to include the RISCV (experimental) target. I noticed that the instructions on the wiki were out of dat because they said to use '-DLLVM_TARGETS_TO_BUILD', but this gave a warning to use `LLVM_EXPERIMENTAL_TARGETS_TO_BUILD` as well (or instead?). So I compiled with these options: cmake -DCMAKE_BUILD_TYPE=MinSizeRel -DCMAKE_C_COMPILER=gcc >

Hi all, I'm currently working on the implementation for LLVM of the RISCV Bit Manipulation ISA extension described by Clifford Wolf in the following presentation: https://content.riscv.org/wp-content/uploads/2019/06/17.10-b_wolf.pdf and the following document: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.90.pdf The aim is to provide the intrinsic functions to the user in

Dear testers, 8.0.0-rc1 was just tagged (from the branch at r351980). It took a little longer than planned, but it's looking good. Please run the test script, share your results, and upload binaries. I'll get the source tarballs and docs published as soon as possible, and binaries as they become available. Thanks, Hans

On Mon, Apr 13, 2020 at 1:16 PM Jon Roelofs via llvm-dev < llvm-dev at lists.llvm.org> wrote: > As an update, after lots of fixes from a number of different people > (thanks everyone!), the current list of false-positives on `ninja > check-llvm` for the more stringent Gotcha A diagnostic is: > > LLVM :: Analysis/CostModel/X86/vselect-cost.ll > LLVM ::

Hi all, I am proposing the integration of a backend targeting the RISC-V ISA. RISC-V is a free and open instruction set architecture that was originally developed at UC Berkeley. Future development of the ISA specification will be handled by the 501(c)(6) non-profit RISC-V Foundation and its members <https://riscv.org/membership/?action=viewlistings>. You can find much more information at