Displaying 20 results from an estimated 700 matches similar to: "I want to update WritingAnLLVMBackend document"
2010 Aug 03
2
[LLVMdev] Creating a backend target -- must I modify include/llvm/ADT/Triple.h ?
I'm having a go at writing an LLVM backend for the WDC 65816. The
documentation page on writing an LLVM
backend<http://llvm.org/docs/WritingAnLLVMBackend.html>gives this
example of target registration:
extern "C" void LLVMInitializeSparcTargetInfo() {
RegisterTarget<Triple::sparc, /*HasJIT=*/false>
X(TheSparcTarget, "sparc",
2008 Nov 21
1
[LLVMdev] Patch for WritingAnLLVMBackend.html
Here's a patch for WritingAnLLVMBackend.html that describes how
instruction operand mapping works based on an IRC chat I had. Can
someone review and apply it?
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2018 Sep 06
2
How to add Loongson ISA for Mips target?
- my old email address.
The ISA_* classes might not be the best choice for this. There's an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or
2020 Jul 14
2
[Beginner] Understanding Tablegen language
On 7/13/2020 21:30, Thomas Lively via llvm-dev wrote:
> Part of the problem is that ISel patterns are like their own DSL inside
> the TableGen DSL, so keywords like "ins", "outs", and "ops" aren't
> keywords at the TableGen level, but rather at the level of the ISel
> system implemented with TableGen. Copying existing patterns and reading
> the
2014 Sep 09
2
[LLVMdev] Machine Code for different architectures
Hi,
We have some DSP architectures (kalimba) which have 24-bits as their
"minimum addressable unit". So this means that the sizeof a char (and
an int and a short for that matter) is 24-bits.
I quickly read the posted link WritingAnLLVMBackend.html but did not
see an obvious answer to the following question:
Is it possible to write a backend that faithfully represents these
2018 Sep 06
3
How to add Loongson ISA for Mips target?
Hi LLVM developers,
GCC[1] is able to use Loongson ISA[2] for instruction selection:
$ cat hello.c
#include <stdio.h>
int main(int argc, char *argv[]) {
printf("Hello World\n");
return 0;
}
$ gcc -O0 -S hello.c
$ cat hello.s
.file 1 "hello.c"
.section .mdebug.abi64
.previous
.nan legacy
.gnu_attribute 4, 1
.abicalls
2012 Jul 06
4
[LLVMdev] New backend
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hello devs,
I'd like to ask for some advise about adding a backend. I followed
the steps at http://llvm.org/docs/WritingAnLLVMBackend.html (also
adding the backend to the configure script, so it compiles (on Linux)
with LLVM 3.1.
However, llvm-build fails with:
llvm[0]: Constructing LLVMBuild project information.
Usage: llvm-build [options]
2017 Jul 07
2
Error in v64i32 type in x86 backend
Thank You.
On Fri, Jul 7, 2017 at 10:03 AM, Craig Topper <craig.topper at gmail.com>
wrote:
> Yes, that error is from instruction selection. I think your legalization
> changes worked fine.
>
> ~Craig
>
> On Thu, Jul 6, 2017 at 8:21 PM, hameeza ahmed via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> also i further run the following command;
2015 Mar 14
2
[LLVMdev] Add a backend
In attempting to add a backend I came across the documentation here:
http://llvm.org/docs/WritingAnLLVMBackend.html
The section on the build system seems to be out of date, or maybe I don't
understand it. I copied the Sparc target to a directory (Foo for the
example), added Foo to the subdirectories list in
llvm\lib\Target\LLVMBuild.txt and to LLVM_ALL_TARGETS in
llvm\CMakeLists.txt. I
2010 Dec 25
4
[LLVMdev] Question of autotools about adding a new target for LLVM
Hello all,
I am a beginner of LLVM and want to add a new Target for LLVM. I follow the
document (http://llvm.org/docs/WritingAnLLVMBackend.html)
to modify autotools/configure.ac. However when I type ./AutoRegen.sh
There is an error that "Your autoconf was not detected as being 2.60"
I download the source of autoconf 2.60 and install it. And there is the
other error that
"Your
2018 Aug 27
2
Transpiler Question
I want to use LLVM as the main component in my compilation process. In
doing so, I know I need to convert a high-level language to another
language (python or a custom syntax.)
The architecture I'm targeting is non-traditional hardware: microfluidic
devices. Microfluidic devices are a specific class of reconfigurable
computing; which don't necessarily adhere to a traditional
2014 Sep 09
3
[LLVMdev] Machine Code for different architectures
Hi Johnny,
Thanks for this - particularly the tip about cfe-dev. I'm currently
trying to coerce lldb to debug these type of architectures (our
current toolchain already outputs good dwarf info). However, I'm
struggling since lldb has just assumes that the size of a byte is
universally 8-bits. At some stage, I *think* at some stage we'd like to
derive a compiler, from the "same
2015 Mar 14
2
[LLVMdev] Add a backend
Yes, llvm::InitializeAllTargetMCs(void) does seem to be autogenerated. It
is _LLVMInitializeFooTargetMC that I can't find documented anywhere.
On Sat, Mar 14, 2015 at 12:05 AM, Anton Korobeynikov <
anton at korobeynikov.info> wrote:
> This function is autogenerated. You need also to change top-level
> configure / cmake files.
>
> On Sat, Mar 14, 2015 at 8:38 AM, Daniel
2014 Mar 28
2
[LLVMdev] How to extract the starting address of each basic block with llvm?
Dear all,
I use the clang frontend to produce the control flow graph of a C program
through
this command:
clang -Xclang -analyze -Xclang -analyzer-checker=debug.DumpCFG test.c
The produced information contains all the basic blocks identified by labels,
e.g. B1, B2, etc. along with their predecessors and successors.
Is there a way to get the starting address of each of these basic block?
I would
2005 Apr 24
0
[LLVMdev] trig language-like code generator generator
On Sun, Apr 24, 2005 at 07:15:03PM +0800, Tzu-Chien Chiu wrote:
> i'd like to know if there is any plan or existing work to add a Aho's
> trig language like code generator generator?
I'm not aware of either the trig language code generator nor any work to
implement it in LLVM.
> "...If you are starting a new port, we recommend that you write the
> instruction
2009 Feb 23
0
[LLVMdev] Creating an LLVM backend for a very small stack machine
On Feb 22, 2009, at 5:43 PM, Wesley J. Landaker wrote:
>
> I would love to see a Kalescope-like tutorial that goes step-by-step
> through
> making a backend. At the very least, I'll be documenting my
> adventure, so
> maybe once I know what I'm doing I can turn it into a tutorial.
Have you seen:
http://llvm.org/docs/WritingAnLLVMBackend.html
If you're targeting
2010 May 27
3
[LLVMdev] TargetDescription string documentation
Hello,
I am trying to find out where the complete documentation for the
TargetDescription string documentation is.
I am reading the tutorial and looking at the sparc backend at the same
time and there are some discrepancies. Therefore the documentation
would be extremely valuable but I can't seem to find it.
In the tutorial it shows the string "E-p:32:32-f128:128:128",
but the real
2012 Jul 06
0
[LLVMdev] New backend
Hello
> I'd like to ask for some advise about adding a backend. I followed
> the steps at http://llvm.org/docs/WritingAnLLVMBackend.html (also
> adding the backend to the configure script, so it compiles (on Linux)
> with LLVM 3.1.
This document is heavily out of date (so, I think it should be removed
/ marked obsolete).
You might grab some information from
2018 Jan 16
2
Exception handling support for a target
> In addition to thanking you for providing the info, I'm writing in the
> hopes that there is some documentation that exists or that someone is
> willing to add to http://llvm.org/docs/ExceptionHandling.html (or a more
> appropriate place with a link there) that would cover the back end
> (target-specific) aspects of EH. Perhaps just a quick description of what a
> target
2014 Sep 10
2
[LLVMdev] Machine Code for different architectures
Hi Patrik,
Thanks for this note. It's encouraging to read there has been some
provision made for non-8-bit bytes. I'm not a compiler/backend expert,
(although maybe I'll need to be soon!), so I won't look at the patches
right now, however may at some stage in the future myself or colleague
may request these patches from yourself.
Yes, our 24-bit architectures have non-power-of-2