similar to: Tail merging "undef" with a defined register: wrong code

I've looked into that and it's not going to be simple, unfortunately. Here's the original example again: --- name: fred tracksRegLiveness: true body: | bb.0: successors: %bb.1, %bb.2 J2_jumpt undef %p0, %bb.2, implicit-def %pc J2_jump %bb.1, implicit-def %pc bb.1: successors: %bb.3 %r0 = L2_loadruh_io undef %r0, 0 PS_storerhabs 0, killed

Yes, immediately after branch folding the code would still behave the same as the original. At the same time, any subsequent optimization may "exploit" the incorrect liveness information to do something bad. If you add -run-pass if-converter, you'll get: # After If Converter # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs BB#0: %R0<def>

On 7/28/2017 1:59 PM, Quentin Colombet wrote: > Hi Krzysztof, > > Thanks for digging into this. > >> On Jul 28, 2017, at 11:08 AM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: >> >> I've looked into that and it's not going to be simple, unfortunately. >> >> Here's the original example again: >> >> --- >>

Hi All, The following code : void hexagon2( int *a, int *res ) { int i = 100; while ( i-- ) { *res++ = *a++; } } gets compiled as a sub-optimal Software loop on LLVM 9.0 instead of a Hardware loop, whereas it was compiled as a Hardware Loop in LLVM 7.0. This is the final assembly code generated by LLVM 9.0 : .text .file "main.c" .globl hexagon2 // --

The Hexagon part is fixed in r364790. -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> LLVM compiler development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Joan Lluch via llvm-dev Sent: Sunday, June 30, 2019 2:04 PM To: llvm-dev <llvm-dev at lists.llvm.org> Subject: [EXT] [llvm-dev] [hexagon][PowerPC] code regression

Hi, I’m hitting a machine verifier error in a trivial testcase which I don’t understand. There are 2 dead defs of the same register: --- name: multiple_connected_compnents_dead tracksRegLiveness: true body: | bb.0: dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec ... The live intervals look OK to me with 1 valno

Hi Venu, FWIW, I have a pass that does copy propagation after RA [1] (currently only within a basic block) that should be enabled some time in the not-too-distant future. It has been reviewed and accepted, but I'm currently working on getting a slight change to the MachineOperand representation [2] that should make the copy propagation change much simpler. I believe this change to

Hi Geoff/Krzyssztof, Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts. Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a

Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but

Hi Venu, This is happening because there is an implicit def of ECX on the COPY instruction. This was an issue on Hexagon as well. Let me give you some background. There are two kinds of implicit defs (and implicit uses, but I'll refer only to defs for brevity): (1) Those that indicate that some physical register (that is not an operand) is modified by a given instruction (EFLAGS is a good

Hi Krzysztof, In one of your earlier emails in this thread you mentioned that you had some changes which add extra aliases for subregisters. Did you mean for X86? And is it extra register units that you added or aliases? I tried adding extra register units for X86 through some changes in CodeGenRegisters.cpp in TableGen but I am seeing a runtime error in one of my test cases possibly due to the

Sadly the latest optimization broke completely everything. The asm code isn't gas compliant. the libFLAC linker script has a typo, disabling the asm optimization and/or altivec won't let a correct build anyway. Instant fixes for the asm stuff: sed -i -e"s:;:\#:" on the lpc_asm.s to load address instead of addis+ori you could use lis and la and PLEASE use the @l(register)

I've had this a long time but haven't submitted it yet. I've tried to mirror the ia32 setup, so there should be a new subdirectory src/libFLAC/ppc . The first two attachments go there. The third is a context diff for src/libFLAC/Makefile.am . I have some more modified files, which I figured I'd submit after the above are checked in and working for somebody other than me. If you

On 02.10.2016 20:03, Ilia Mirkin wrote: > On Sun, Oct 2, 2016 at 1:58 PM, Tobias Klausmann > <tobias.johannes.klausmann at mni.thm.de> wrote: >> Previously we'd end up with an unnecessary mov for the thirs immediate value. >> >> total instructions in shared programs : 851881 -> 851864 (-0.00%) >> total gprs used in shared programs : 110295 -> 110295

define xen paravirtualized instructions for hand written assembly code. Signed-off-by: Yaozu (Eddie) Dong <eddie.dong at intel.com> Signed-off-by: Isaku Yamahata <yamahata at valinux.co.jp> Cc: Akio Takebe <takebe_akio at jp.fujitsu.com> --- include/asm-ia64/xen/inst.h | 447 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 447 insertions(+), 0 deletions(-) create

Dear R helpers,   I have following input files. (Actually they are more than 10 rates but here i am considering only 2 rates to write my problem)   rate1.csv min1        max1            min2          max2          min3           max3 1.05        1.30               1.30          1.65             1.65          1.99   rate2.csv min1        max1            min2          max2          min3          

Dear list, After reading different mails, blogs, and tried a few different codes without any success, I am asking your help! I have the following data frame where each row represent a survey unit with the following variables: > names(RV09) [1] "record.t" "trip" "set" "month" "stratum" "NAFO" [7]

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi Chris, Chris Lattner wrote: > On Fri, 2 Feb 2007, Nicolas Geoffray wrote: > > > Some meta comments: > > 1. Please don't change PPC -> llvmPPC. I assume that you did this because > PPC is a #define in some system header. Please just add a '#undef PPC' > where appropriate to make this unneeded. > OK > 2. The X86 backend has the