Displaying 20 results from an estimated 1000 matches similar to: "Value"
2017 Jul 20
3
Value
Thank you! I wanted to use the right part of the instruction ,
%a = alloca i32, align 4 - %a here , but I don't quite understand the
difference between Instruction object and Value object of a, which is used
further , and in this case :
%1 = alloca i32, align 4 - I also wanted to use %1 and in this case the
only possibility is Instruction object.
2017-07-20 15:32 GMT+02:00 Evgeny Astigeevich
2017 Jul 20
2
Value
I am performing the bit analysis, so actually I want to propagate
information about bits from operands to the instruction (the result of
instruction), and every time I access the Instruction first , than get the
operands, then access to the next instruction.
That was the only problem, that I keep a map from Instruction to bit info
and was confused, is Instruction, that I am putting to map, is the
2017 Aug 11
2
PHI nodes and connected ICMp
Thank you for your answer! I tested your example, yes, perhaps I should
preserve some kind of tree to parse this start and end expressions for
induction variable... I was surprised, that SCEV cannot compute the
tripcount here. I thought, that all linear and maybe expressions with
multiplication are suitable for analysis.
2017-08-10 19:30 GMT+02:00 Sanjoy Das <sanjoy at google.com>:
> Hi
2017 Aug 13
2
PHI nodes and connected ICMp
To continue this topic:
sometimes SCEV's behavior is rather controversial : for loops with i
changing as i \=2 for example, he can't figure what the type of expressions
is, but surprisingly can determine max trip count. Shouldn't it be able to
detect or not detect these parameters at the same time?
2017-08-11 15:56 GMT+02:00 Anastasiya Ruzhanskaya <
anastasiya.ruzhanskaya at
2017 Aug 09
4
ind variable
This support was removed years ago from indvars. We don't need canonical
induction variables any more as all analysis are done on SCEVs. The SCEV
generator can transform them even without the need for explicit
canonical induction variables.
Best,
Tobias
On Wed, Aug 9, 2017, at 14:23, Anastasiya Ruzhanskaya via llvm-dev
wrote:
> The files of this strange pass are described here
>
2017 Sep 02
3
getelementptr
Ok, thank you. I have also one question about getelementptr. In different
versions of clang I see that sometimes array[i][i] is preceded by two
getelementptr instructions and sometimes only by one - with an already
complex index.
2017-09-01 12:50 GMT+02:00 David Chisnall <David.Chisnall at cl.cam.ac.uk>:
> On 1 Sep 2017, at 11:44, Anastasiya Ruzhanskaya via llvm-dev <
> llvm-dev
2017 Nov 10
5
[RFC] Enable Partial Inliner by default
Hi Graham,
Thank you for offering help. I am trying to create a reproducer. The problem is that the crashes happen whilst LTO is used. One thing I am sure about IR is broken at compile time.
Thanks,
Evgeny
From: Graham Yiu <gyiu at ca.ibm.com>
Date: Friday, 10 November 2017 at 16:09
To: Evgeny Astigeevich <Evgeny.Astigeevich at arm.com>
Cc: "junbuml at codeaurora.org"
2017 Aug 07
2
vrp
I am primarily interested in phi nodes and their induction variables, in
ValueTracking file there is an analysis of them, but if the upper bound is
inf, it is not working?
2017-08-07 11:41 GMT+02:00 Anastasiya Ruzhanskaya <
anastasiya.ruzhanskaya at frtk.ru>:
> So, it is not supported to determine by this instruction : %cmp = icmp slt
> i32 %i.03, 99,
> that %i.03 = phi i32 [ 0,
2017 Jan 27
2
Reversion of rL292621 caused about 7% performance regressions on Cortex-M
Hi Wei,
Thank you for information.
Please let me know about any progress in fixing the failures.
I can help with checking that the final patch gives the same level of performance improvements.
Kind regards,
Evgeny Astigeevich
Senior Compiler Engineer
Compilation Tools
ARM
> -----Original Message-----
> From: Wei Mi [mailto:wmi at google.com]
> Sent: Friday, January 27, 2017 6:20 PM
2017 Sep 02
2
getelementptr
No.
It would be helpful to understand what you are trying to accomplish
overall, which may help people give you details about the best way to
accomplish it.
For example, if you are trying to understand or recover array indexes from
GEP's, that is non-trivial.
On Sat, Sep 2, 2017 at 3:53 AM, Anastasiya Ruzhanskaya via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Is there a way
2017 Jul 17
2
value range propagation
Hello,
I wonder if llvm has pure range propagation pass. Is correlated value
propagation that one? It seems that it is not directly deals with ranges.
Maybe there any passes that simply contain some information about value
ranges?
Will symbolic value range propagation be done in some time?
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2017 Aug 10
4
PHI nodes and connected ICMp
Hi!
By only two cases I mean , that in exiting block when computing the
condition related to PHI node I can expect only icmp on one of incoming
values or on phi node itself... I tried to come up with some more complex
examples but I always receive only these two cases, that is why I am asking.
This problem still relates to the problem of all induction, cumulative and
so on variables in loop. SCEV
2017 Jan 27
2
Reversion of rL292621 caused about 7% performance regressions on Cortex-M
Hi Evgeny,
Quentin and Matthias found it was a problem about subreg live range
update and will push a fix soon
(http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170123/424126.html).
Thanks,
Wei.
On Fri, Jan 27, 2017 at 10:35 AM, Wei Mi <wmi at google.com> wrote:
> Sure. Will keep you posted.
>
> Thanks,
> Wei.
>
> On Fri, Jan 27, 2017 at 10:31 AM, Evgeny
2017 Nov 10
2
[RFC] Making .eh_frame more linker-friendly
> But if we still need to deal with CIEs and generate .eh_frame_hdr in a special way,
> does it make sense to make this change to simplify only a small part of a linker?
For huge C++ projects this could improve link time if GC is a bottleneck. It will also improve eh_frame_hdr build time because you don’t spend time on parsing garbage. However a linker will have to have two versions of GC:
2017 Jul 25
2
loop canonical variables
Hi Anastasiya,
If it fits you use case, you can consider walking the loop header and
calling getSCEV() on all of the PHI nodes in the header. This will
give you a SCEV* which should be easier to analyze than manually
inspecting PHI cycles.
Thanks!
-- Sanjoy
On Tue, Jul 25, 2017 at 11:42 AM, Michael Kruse via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> 2017-07-25 19:32 GMT+02:00
2017 Jan 23
2
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
Confirm there is no change in IR if the hack is disabled in the sources.
David wrote that these instructions are created by SCEV.
Are other targets affected by the changes, e.g. X86?
Kind regards,
Evgeny Astigeevich
Senior Compiler Engineer
Compilation Tools
ARM
From: Sanjay Patel [mailto:spatel at rotateright.com]
Sent: Sunday, January 22, 2017 10:45 PM
To: Evgeny Astigeevich
Cc: llvm-dev; nd
2017 Nov 10
2
[RFC] Making .eh_frame more linker-friendly
Hi Igor,
> It sounds like the linker has to be aware of the .eh_frame section details to be able to generate .eh_frame_hdr and eliminate duplicate CIEs, right?
Yes, a linker needs some details but not all of them. It needs to know sizes of records and initial locations (PC Begin) to find out which functions FDEs belong to.
> So, is there any difference whether it knows that in one place
2017 Aug 21
2
Combining passes
Hello,
this is a question, concerning cmake lists configuration. I am trying to
link together two llvm passes, but they still should be as two modules. So:
passA - A.so
passB - B.so
passB should use passA , so I sould use target_link_libraries ( and of
course, I have included useAnalysis in passB) . But I can't link libraries
that are build as Modules, so I tried to create two libraries at
2017 Jan 24
3
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
> On Jan 24, 2017, at 7:18 AM, Sanjay Patel <spatel at rotateright.com> wrote:
>
>
>
> On Mon, Jan 23, 2017 at 10:53 PM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote:
>
>> On Jan 23, 2017, at 3:48 PM, Sanjay Patel via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>
2017 Jan 27
2
Reversion of rL292621 caused about 7% performance regressions on Cortex-M
Hi Wei,
Your reversion of rL292621 caused about 7% performance regressions in our benchmark on Cortex-M7/M4.
In your commit comment I see it causes build bot failures.
What kind are the failures? Compiler crashes or incorrect code generation? Will you fix them?
We are interested in the changes because of performance improvements they give.
Kind regards,
Evgeny Astigeevich
Senior Compiler