similar to: [LLD] Linker Relaxation

Here's an example using the gcc toolchain for embedded 32 bit RISC-V (my HiFive1 board): #include <stdio.h> int foo(int i){ if (i < 100){ printf("%d\n", i); } return i; } int main(){ foo(10); return 0; } After compiling to a .o with -O2 -march=RV32IC we get (just looking at foo) 00000000 <foo>: 0: 1141 addi sp,sp,-16

By the way, since this is an optional code relaxation, we can think about it later. The first thing I would do is to add RISC-V support to lld without code shrinking relaxations, which I believe is doable by at most a few hundreds lines of code. On Wed, Jul 12, 2017 at 3:21 AM, Rui Ueyama <ruiu at google.com> wrote: > On Tue, Jul 11, 2017 at 9:14 PM, Bruce Hoult via llvm-dev < >

Hi, On Wed, Jul 12, 2017 at 2:21 AM, Rui Ueyama via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Thanks, Bruce. This is a very interesting optimization. > > lld doesn't currently have code to support that kind of code shrinking > optimization, but we can definitely add it. It seems that essentially we > need to iterate over all relocations while rewriting

Hi, I have kept working on this and found the following (as llvm 3.5): 1) In the function MCObjectStreamer::EmitInstruction there is a check for the instruction being relaxable or not: if (!Assembler.getBackend().mayNeedRelaxation(Inst)) { EmitInstToData(Inst, STI); return; } At this stage, the instruction as been already selected to be ARM::ADR. The call to mayNeed 2015-07-07 18:06

> ~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr > -melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o Ok, this way you're generating code for x86 > /usr/lib/crti.o > /usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o > -L/usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0  -L/usr/local/lib -lgcc > --as-needed -lgcc_s --no-as-needed -lc -lgcc

Sorry for not explaining well. After compiling with g++-cross g++-cross -c a.c I do link using this command /gold_binutils/build/gold/ld-new -plugin ~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr -melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o /usr/lib/crti.o /usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o

On 25 January 2018 at 15:38, ORiordan, Martin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Hi LLVM-Devs, > > I am considering switching to using 'llvm-lld' instead of Gnu 'ld' in a future revision of our out-of-tree target, and I am wondering is there a getting started guide for how to go about extending 'llvm-lld' to support an additional target. I

Hi list-members can anybody tell me why > pairwise.t.test(val, fac) produces an empty p-table. As shown below: Pairwise comparisons using t tests with pooled SD data: val and fac AS AT Fhh Fm Fmk Fmu GBS Gf HFS Hn jAL Kol R_Fill AT - - - - - - - - - - - - - Fhh - - - - - - - - - - - - - Fm - - - - - - -

Hi, In our (non-C) compiler we use setjmp/longjmp to implement exception handling. For the initial implementation LLVM backend, I'm keeping that model. In order to ensure that changes performed in a try/setjmp==0 block survive the longjmp, the changes must be done via volatile operations. Given that volatility is a property of individual load/store instructions rather than of memory slots in

i have this code typedef long long L; typedef integer I; void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) { va_list select; va_start (select, p4); report( va_arg(select,L) ); report( va_arg(select,I) ); report( va_arg(select,L) );

Hi all, I have reached the relocation phase of my backend implementation and I'm having some trouble. The LLVM code I'm trying to compile is this: %struct.Date = type { i32, i32, i32 } @date = global %struct.Date { i32 2012, i32 10, i32 120000 }, align 4 ; Function Attrs: nounwind define i32 @foo() #0 { %1 = load i32, i32* getelementptr inbounds (%struct.Date, %struct.Date* @date, i32

To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered. - Matthias > On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote: > > I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet. > > The

Thanks. This is making a lot more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32

On Mon, Sep 19, 2016 at 4:42 AM, Jonas Maebe <jonas-devlists at watlock.be> wrote: > Reid Kleckner wrote: > > On Fri, Sep 16, 2016 at 10:13 AM, Jonas Maebe via llvm-dev > > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > > > model. In order to ensure that changes performed in a try/setjmp==0 > > block survive

I created a DomU with a dedicated network connection script path=''/usr/lib/xen/scripts/vif-dedicated'' Having run the virtual machine I now destroy the domain, undefine it, change the script to script path=''/usr/lib/xen/scripts/vif-vnic'' define the domain and try to start it. This fails. If I change the assigned MAC address the newly defined virtual

Hi all, I'm trying to implement the same branch relaxation mechanism implemented in CodeGen in the MC layer of RISCV.   beqz t1, L1   =>   bnez t1, L2   j L1 That's because LLVM does not apply the CodeGen optimizations when compiling directly from assembly code. What I'd like to do would be to add a pass that does that on the MC instructions or at least to find a way to

Hi, I noticed that klibc started crashing on 64-bit MIPS and in my quest to fix the bug I got a bit carried away and fixed a few other things as well. Here are various miscellaneous MIPS patches, although the first patch is the important one. Thanks, James *** BLURB HERE *** James Cowgill (5): mips64: compile with -mno-abicalls mips: use -Ttext-segment when linking shared library

Hi LLVM-Devs, I am considering switching to using 'llvm-lld' instead of Gnu 'ld' in a future revision of our out-of-tree target, and I am wondering is there a getting started guide for how to go about extending 'llvm-lld' to support an additional target. Thanks, MartinO -------------------------------------------------------------- Intel Research and Development

I have created a small ll file to reproduce the problem. I used the intrinsic function llvm.arm.space to introduce space between the beginning of the code and the jump table. If the first argument of llvm.arm.space is higher than INT_MAX ( *2147483647)*, then the bug is hit. Lower or equal to that value, it passes. It looks like a precision issue. Does this sound familiar to someone? ; ModuleID =

Hi everyone The c code is like below extern int function_0(int, int); int main(){ return function_0(8, 9); } I compile it as below llvm-gcc main.c -emit-llvm -c -O3 -o main.bc llc main.bc -relocation-model=static -march=mips -O0 -o main.s It seems no argument is provided to function_0 ... addiu $sp, $sp, -8 sw $ra, 0($sp) jal function_0