Displaying 20 results from an estimated 300 matches similar to: "Using new types v32f32, v32f64 in llvm backend not possible"
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Thank you so much. it run fine.
Can you please resolve following issue;
I now have support for v2048i32
but my backend supports v64i32
so ultimately v2048i32 needs to be split into 32 v64i32 instructions. the
only difference between 2 is if its orginally v2048i32 i want my registers
assignment from REG_A set. if its v64i32 originally, then i want registers
from set REG_B.
How to accomplish
2017 Jul 12
2
Using new types v32f32, v32f64 in llvm backend not possible
I would be very grateful if you specify whether there is some way to
allocate registers (different order) / from different register sets to the
same instruction based on the vector width/ no of iterations.
I have tried several alternatives but could not succeed.
Also I have asked this question many times but no one responds.
Is there something wrong with this??
Kindly guide me.
Thank You
On
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
hello,
i need to use v32i32 and v32f32 in store instructions.
I defined my register as;
def VRR128 : RegisterClass<"X86", [v32i32, v32f32],
1024, (add R_0_V_0, R_1_V_0, R_2_V_0)>;
def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst,
VRR128:$src),
"STORE_DWORD\t{$src, $dst|$dst, $src}",
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
Thank You.
How to do the same for add please see the following; it gives duplication
error.
def VADD : I<0x0E, MRMDestReg, (outs VRR128:$dst), (ins VRR128:$src1,
VRR128:$src2),"VADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set
VRR128:$dst, (add VRR128:$src1, VRR128:$src2))]>, TA;
def : Pat<(add VRR128:$src1, VRR128:$src2), (VADD VRPIM128:$src1,
VRPIM128:$src2)>;
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
Thank You.
But can we use same register class for fadd as well,
is this instruction correct?
def VFADD : I<0x0E, MRMDestReg, (outs VRR128:$dst), (ins VRR128:$src1,
VRR128:$src2),"VFADD\t{$src1, $src2, $dst|$dst, $src1, $src2}", [(set
VRR128:$dst, (fadd VRR128:$src1, VRR128:$src2))]>, TA;
On Tue, Jul 11, 2017 at 9:00 PM, Craig Topper <craig.topper at gmail.com>
wrote:
>
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
Please tell me whether the following implementation is correct.....
My target supports 64 bit mask means immediate(0-2^63)
I have implemented it but i dont know whether its correct or not. Please
see the changes below that i have made in x86isellowering.cpp
static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int>
Mask,
MVT VT,
2018 Jul 24
2
KNL Vectorization with larger vector width
Thank You.
Right now to see the effect i did following changes;
unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasAVX512())
return 65536;
here i changed 512 to 65536. Then in loopvectorize.cpp i did following;
assert(MaxVectorSize <= 2048 && "Did not expect to pack so many elements"
" into
2020 Jun 30
5
[RFC] Semi-Automatic clang-format of files with low frequency
I 100% get that we might not like the decisions clang-format is making, but
how does one overcome this when adding new code? The pre-merge checks
enforce clang-formatting before commit and that's a common review comment
anyway for those who didn't join the pre-merge checking group. I'm just
wondering are we not all following the same guidelines?
Concerns of clang-format not being good
2018 Jul 24
2
KNL Vectorization with larger vector width
Hello,
I need help here. I am able to adjust the vector width through
WidestRegister value. When number of iterations=31 and I set vector
width=32 it gives <16xi32> and <8xi32> instructions.
However if i replicate same behavior with number of iterations=63 and I
set vector width=64, no vector instructions are emitted. it should do as
previous and gives <32xi32> and
2018 Jul 23
2
KNL Vectorization with larger vector width
Thank You. I got it. Version issue.
TTI.getRegisterBitWidth(true)
How to put my target machine info in TTI?
Please help.
On Mon, Jul 23, 2018 at 11:33 PM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 10:49 AM, hameeza ahmed via llvm-dev wrote:
>
> Thank You.
>
> But I cannot find your mentioned function
2010 Jul 17
2
[LLVMdev] v16i32/v16f32
I tried adding them in my backend however I run into the assertion
assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
ExtType < array_lengthof(LoadExtActions) &&
"Table isn't big enough!");
What does the assertion mean ?
thanks for all help!!
shrey
On Wed, Jul 14, 2010 at 6:56 PM, Eli Friedman <eli.friedman at
2010 Jul 17
0
[LLVMdev] v16i32/v16f32
On Fri, Jul 16, 2010 at 5:14 PM, shreyas krishnan <shreyas76 at gmail.com> wrote:
> I tried adding them in my backend however I run into the assertion
>
> assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
> ExtType < array_lengthof(LoadExtActions) &&
> "Table isn't big enough!");
>
> What does the
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
Here basically my problem is vector width since i have used v64i32 in my
backend. now if vector width=64. i want the Reg_B class registers to be
assigned and if vector width=2048 i want Reg_A registers to be assigned to
instruction.
Should i incorporate the solution in lowering stage? some thing like;
addRegisterClass(MVT::v2048i32, &X86::Reg_B);
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I wanted to inform that I fixed the bug from the previous email.
The main reason for the bug was that I thought that the SDNode masked_gather is
returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult
to follow, error: "Assertion `New->getNumTypes() == 1").
masked_gather returns 2 values because:
// SDTypeProfile -
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I fixed the bug reported in the previous post on this thread
(<<llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&,
llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <=
MMO->getSize() && "Size mismatch!"' failed.>>)
The problem with this strange error reported comes from
2015 Jan 15
2
[LLVMdev] Overloaded intrinsics: name explosion
Hi,
So, we currently have gc.result.int, gc.result.float. gc.result.ptr,
gc.relocate, and gc.statepoint. gc.statepoint's signature is fine with
a iPTRAny as the first argument. gc.result is in trouble, because none
of the signatures admit even a simple array of integers, and there's
no aAny. And certainly no vectors. So we can get a gc.result.vector to
add to this mess, and admit [1] to
2012 Jul 26
2
[LLVMdev] Why is this assertion here?
I'm trying to understand why this assertion is here.
LegalizeAction
getCondCodeAction(ISD::CondCode CC, EVT VT) const {
assert((unsigned)CC < array_lengthof(CondCodeActions) &&
(unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
"Table isn't big enough!");
LegalizeAction Action = (LegalizeAction)
2012 Jul 26
2
[LLVMdev] RFC: CondCodeActions refactor (was RE: Why is this assertion here?)
On Thu, 26 Jul 2012 21:15:35 +0000
"Villmow, Micah" <Micah.Villmow at amd.com> wrote:
> Well, I found out the reason why this assert is here, and this is
> problematic.
>
> CondCodeActions only supports up to 32 different value types. Since
> we are past 32, what LLVM has is broken.
>
> Currently the 4 different Legalize states are stored in successive
>
2017 Jul 10
2
Conditional Register Assignment based on the no of loop iterations
hello,
i have a situation where i have to assign the registers to instructions
based on the loop iterations.
for eg..
the registers are:
R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3,
R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3,
R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3.
These registers defined in object Reg_A
These are total 12 registers. will use them contiguously, here i define it
in above mentioned order i.e
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it.
I currently have some serious problems with TableGen - it gives an assertion failure: