similar to: LLVM's loop strength reduction module

Hi Raghavan, I concur no specific docs. What do you want to know specifically? Cheers, -Quentin > On Jul 5, 2017, at 11:16 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > AFAIK, no official doc. > You can probably get better help if you ask specific questions (which part of the code you don't understand). > > On Thu, Jul 6, 2017 at 9:53

Hi, Sorry I took a long time to reply as it took me some time to get some understanding of the code even to ask some specific questions (I have a test case in which LSR does not kick in and wanted to understand the code to figure out why it was not kicking in). Here are some specific questions I have: 1) It appears that LSR works only for the inner-most loop. Is this correct? Can you tell

Hi, Just to clarify I am looking for a whole machine function analysis not just something restricted to within a machine basic block. Thanks. Regards, Venu. From: Raghavan, Venugopal Sent: Saturday, September 02, 2017 12:56 PM To: llvm-dev at lists.llvm.org Subject: Reaching definitions on Machine IR post register allocation Hi, Given a definition of a register by a machine instruction in

Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but

Hi Krzysztof, In one of your earlier emails in this thread you mentioned that you had some changes which add extra aliases for subregisters. Did you mean for X86? And is it extra register units that you added or aliases? I tried adding extra register units for X86 through some changes in CodeGenRegisters.cpp in TableGen but I am seeing a runtime error in one of my test cases possibly due to the

Hi Geoff/Krzyssztof, Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts. Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a

Hi Venu, FWIW, I have a pass that does copy propagation after RA [1] (currently only within a basic block) that should be enabled some time in the not-too-distant future. It has been reviewed and accepted, but I'm currently working on getting a slight change to the MachineOperand representation [2] that should make the copy propagation change much simpler. I believe this change to

Hi Venu, This is happening because there is an implicit def of ECX on the COPY instruction. This was an issue on Hexagon as well. Let me give you some background. There are two kinds of implicit defs (and implicit uses, but I'll refer only to defs for brevity): (1) Those that indicate that some physical register (that is not an operand) is modified by a given instruction (EFLAGS is a good

Hi, I was interested in trying out LLVM BOLT and generated profile data using Linux perf using the following: perf record -e cycles:u -o perf.data <command> This is without the use of LBR so I understand the performance improvements may not be much but this was more for becoming familiar with BOLT's commands. I then run: perf2bolt -nl -p perf.data -o perf.fdata <binary> and I

Surprised to know that backward compatibility is not honored across the tools. (i.e. you can read old .bc but NOT old .ll files) Supporting latter is more useful, IMO, because then I wouldn't have to modify all my sources. And who are "we" here? On Fri, Aug 12, 2016 at 7:21 PM, Tim Northover <t.p.northover at gmail.com> wrote: > On 12 August 2016 at 06:42, Madhur

Hi, For my input file I think that llvm-as is encoding an instruction incorrectly. Is there any way to dump the numerical representation of input textual LLVM IR on terminal? "-f" option to llvm-as did not help. -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar

Hi, How does LLVM identify induction variables of a loop? Is the algorithm based on SSA graphs? I have a complicated loop and I need to do some analysis around it. Can anyone please point me to source of identification part? -- *Disclaimer: Views, concerns, thoughts, questions, ideas expressed in this mail are of my own and my employer has no take in it. * Thank You. Madhur D. Amilkanthwar

Well, I was hinting at LLVM_DEBUG messages. You can pretty much dump all "actions" Tablegen would take to process a .td file, which should suffice, IMO. On Wed, Aug 5, 2020 at 5:59 PM Paul C. Anagnostopoulos <paul at windfall.com> wrote: > Your reply suggests that there is a way to see debug messages from > TableGen. Is that what you meant? If so, can you explain how that

Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org>於 2020年8月9日 週日，上午1:53寫道： > Hi Paul, > I hope you have gone through > https://llvm.org/docs/Contributing.html#how-to-submit-a-patch. > > Generally, I would do 'git add' on the new file. 'git diff' should show me > the newly added file. Further, I'd just do 'arc diff' and this should

Thank You.. I am asking to generate directly PTX code automatically or by directives without involvement of CUDA. This way, I am talking about avoiding source to source compiler approach where c code is converted automatically into CUDA, instead I am saying directly to convert C code to PTX assembly. On Tue, Dec 11, 2018 at 12:19 PM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote:

Hi all, I have the below input define i32 @myCas(i32* %ptr, i32 %cmp, i32 %val) #0 { entry: %0 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %val seq_cst %1 = extractvalue { i32, i1 } %0, 0 ret i32 %1 } When I provide this input file to llvm-as 3.6 I get the error a.ll: error: Expected ordering on atomic instruction %1 = extractvalue { i32, i1 } %0, 0 This is because instruction syntax

I am ready to submit my first real submission for review with Phabricator. Please forgive my meager knowledge of Git. I did a 'git diff' to generate the diff file. The contents look good. However, there is one new file, a TableGen test file. How do I get that file included in the diff, or otherwise included in the submission?

On Tue, Oct 13, 2020 at 10:47 AM Madhur Amilkanthwar <madhur13490 at gmail.com> wrote: > What do you guys think about the below enhancements? > > 5. !getdagrestype(dag [, index]) - Returns type of result value. If the DAG computes multiple values then return type of 'index'th result. > > 6. !setdagrestype(dag target_dag, type T [, index]) - Set return type of

Adding -debug to a -gen-dag-isel run can also print useful information about the parsed patterns. On Wed, Jul 15, 2020 at 10:44 AM Matt Arsenault via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > > On Jul 15, 2020, at 13:33, Rotate Right via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > Is there a backend to Tablegen which can dump a map of

> On Apr 11, 2017, at 10:25 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I am interested in knowing more. > 1. What benchmarks does LLVM community use for compile-time study? I see CTMark, but is that the only one being analyzed? CTMark is not cast in stone. Its purpose is for the community to have a trackable proxy for the overall llvm test