similar to: Proposal: On re-purposing/reorganizing MIR sigils ('&', '$', '%').

When we discussed this our line of thought was like this: - LLVM IR already uses %name for SSA values which is closer to what a vreg is than to what a physreg is. It would be neat to draw that parallel to llvm IR. - We wanted another sigil for physregs so they are easy to differentiate from vregs to allow people to differentiate vregs/physregs even if they don't know all the physreg names of

Can we use %% for vregs? Seems slightly easier to remember %/%% than $/%. Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. It's all a bikeshed, but being more consistent with assembly is probably a win. -- Sean Silva On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < llvm-dev at

On Mon, Jan 8, 2018 at 2:27 PM, Matthias Braun <mbraun at apple.com> wrote: > When we discussed this our line of thought was like this: > > - LLVM IR already uses %name for SSA values which is closer to what a vreg > is than to what a physreg is. It would be neat to draw that parallel to > llvm IR. > - We wanted another sigil for physregs so they are easy to differentiate

We had some additional discussion on this. There is a lot of concern generally about post-RA passes which do not expect to have to handle virtual registers; specifically if they unexpectedly start seeing virtual registers, or if they work today but start making assumptions in the future. We discussed considering a mechanism that would require MachineFunctionPasses to "opt-in" and declare

Here are 2 patches, which are independent of each other. The first splits PrologEpilogInserter into 2 parts : http://reviews.llvm.org/D16481 After looking at the code I thought it made more sense for the major split to include whether callee-saved register spills are supported. So for non-virtual targets, virtual registers are not supported and scavenging is optionally supported, and vice versa

> On Jan 22, 2016, at 1:23 PM, Matthias Braun <mbraun at apple.com> wrote: > >> >> On Jan 22, 2016, at 12:29 PM, Derek Schuff <dschuff at google.com <mailto:dschuff at google.com>> wrote: >> >> Here are 2 patches, which are independent of each other. >> >> The first splits PrologEpilogInserter into 2 parts :

What's the best way to get an SDNode through to DAG scheduling without getting mangled during Lowering/ISel? When should subregs be flattened to actual registers: AsmPrinter? Somewhere in LiveIntervals, during RegAlloc? Is there are common API used to turn vregs into physregs that could be changed to flatten any subregs in a central location? -- Christopher Lamb

To say this first: This whole discussion about using virtregs until emit or having growable physregs is hard to argue without actually having experience trying to go either way. Problems when using virtregs throughout the backend until emit time: - The MC layer is using MCPhysReg (which is an uint16_t) and would need retrofitting to support virtregs - VirtRegs are assumed to have a definition,

On Mon, 16 Apr 2007, David Greene wrote: >> Yep, this is the one I was thinking of. It is available online here: >> http://www.cs.rice.edu/~keith/LACSI/pldi02.pdf > > I was just looking at this today. One thing that strikes me about > all these papers I've read on the topic is that no one seems to > consider the interaction of coalescing with spilling. By definition

> On 29 Sep 2020, at 09:28, Quentin Colombet <qcolombet at apple.com> wrote: > > + Daniel who added the MCRegister class. > > Ah sorry, I replied too fast. > I mixed up MCPhysReg with MCRegister. > > I was not aware we had such class. > > From a look at it, MCRegister are essentially the same thing as Register. I am guessing that the difference is Register

Yes so long as you're including the invalid space too (IIRC it matters for DBG_VALUE in particular) the reason I didn't do that is that there's a lot more ctors than consumers of MCRegister. It seemed cheaper to do the checks when they're consumed and pretty much every consumer I encountered started with `assert(Reg.isPhysicalRegister() && ...)`. > On 29 Sep 2020, at

On 1/7/2015 8:59 AM, Chandler Carruth wrote: > > Essentially, I think target-independent optimizations are still > attractive, but we might want to just force them to go through an > actual target-implemented API to interpret the scopes rather than > making the interpretation work from first principles. I just worry > that the targets are going to be too different and we may

(gah, this turned into a huge digression, sorry) The implicit numbering of BB's seems to be a pretty frequent issue for people. Surprisingly, the issue boils down to simply changing the IR asm (.ll file) syntax so that it can have "unnamed BB's" in a recognizable way that fits in with how unnamed values work (the asmprinter makes an effort to print a comment with the BB number,

> On 29 Sep 2020, at 11:13, Mircea Trofin <mtrofin at google.com> wrote: > > > > On Tue, Sep 29, 2020 at 11:09 AM Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > Yes so long as you're including the invalid space too (IIRC it matters for DBG_VALUE in particular) the reason I didn't do that is that

Thanks for the lecture :) But I was not planning on changing a single line in LLVM/Clang. I stick to the documentation until I've learned to swim, perhaps even forever. Ah, now I see. You thought I meant "should I modify the code to do this or that." I only meant to change the documentation. Please refer to the patch I've sent on LLVM-commits. That's about what I had

On Tue, Nov 26, 2013 at 9:58 PM, Mikael Lyngvig <mikael at lyngvig.org> wrote: > Thanks for the lecture :) But I was not planning on changing a single > line in LLVM/Clang. I stick to the documentation until I've learned to > swim, perhaps even forever. Ah, now I see. You thought I meant "should I > modify the code to do this or that." I only meant to change

On Jun 11, 2007, at 6:14 PM, Christopher Lamb wrote: > > What's the best way to get an SDNode through to DAG scheduling > without getting mangled during Lowering/ISel? What do you mean by "mangled"? Please clarify. > > When should subregs be flattened to actual registers: AsmPrinter? > Somewhere in LiveIntervals, during RegAlloc? You mean turning part of a

Finally I noticed something suspect: [2008-08-19 09:11:25] [DEBUG] DAO_Articles::add_xindex() - document added id : 255, title : Gli anelli con sigil... this is a debug line from my application, add_xindex function simply adds the document to xapian database, the error always happens when I try to add an article with id = 255, this can not be a casualty (I also tried to change the order of

I'm forwarding this to llvmdev so it doesn't get lost in the sea of commits... -Dave ---------- Forwarded Message ---------- Subject: Re: [llvm-commits] [llvm] r48521 - in /llvm/trunk: include/llvm/CodeGen/LiveVariables.h lib/CodeGen/LiveVariables.cpp test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll test/CodeGen/X86/x86-64-ret0.ll

Without ANY intent of offending anybody, I simply don't like C++. I did code in it for some 12 years back from 1990 to 2002, but then I left it behind with a feeling of happiness. The main reason I am _trying_ to make a new language is that I hope to one day come up with something that can help retiring C++. I love C# but that language is yet too slow for many demanding problem domains.