similar to: Immediates in intrinsics

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

Copy Ii32 in X86InstrFormats.td rename to Ii64 and change Imm32 to Imm64. Instantiate your instruction inheriting from Ii64. Pass RawFrm to the form parameter. Initial documentation for the encoding system is attached. ~Craig On Wed, Mar 28, 2018 at 4:50 PM, Gus Smith via llvm-dev < llvm-dev at lists.llvm.org> wrote: > I am attempting to create an instruction which takes a single

On Wed, Jan 16, 2013 at 12:04:52PM -0500, Stephen Checkoway wrote: > > On Jan 16, 2013, at 10:07 AM, Brad Smith <brad at comstyle.com> wrote: > > > I was wondering if someone with more familiarity with MC > > on X86 could consider looking into adding support for > > the hyphenated versions of the VIA Padlock instructions? > > > Take a look at

On Jan 16, 2013, at 10:07 AM, Brad Smith <brad at comstyle.com> wrote: > I was wondering if someone with more familiarity with MC > on X86 could consider looking into adding support for > the hyphenated versions of the VIA Padlock instructions? Take a look at llvm/lib/Target/X86InstrSystem.td perhaps. -- Stephen Checkoway

I was wondering if someone with more familiarity with MC on X86 could consider looking into adding support for the hyphenated versions of the VIA Padlock instructions? If anyone is up for it there are details within these two bug reports.. http://www.llvm.org/bugs/show_bug.cgi?id=8556 http://www.llvm.org/bugs/show_bug.cgi?id=10266 -- This message has been scanned for viruses and dangerous

>>> You shouldn't have to add new classes to the .td file, just modify >>> printOp for your asmprinters. >> >> I dont think printOp is virtual and therefore cannot be overriden ? > > Why does it need to be virtual? No 'intel' printers want % signs. The GAS intel code generator generates percents, look at the X86InstrInfo.td file it is full of

Hi Nemanja, I'm attaching a patch that builds on D54583 and implements what we discussed on IRC earlier today. Particularly: * Make LowerCallTo() a virtual function, so it can be wrapped by a subclass. * Implement LowerCallTo() in PPCTargetLowering to wrap TargetLowering::LowerCallTo() and legalize the return node when targeting SPE. * Augment PPCTargetLowering::LowerCall_32SVR4() to

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Aside from the fact that you're checking for i64 specifically instead of generally checking for illegal types, how much of this is really PPC specific? Would this be a reasonable enhancement to the SDAG logic in general? -Hal On 1/4/19 8:03 AM, Nemanja Ivanovic wrote: The changes seem fine to me. I don't think this is excessively intrusive and it accomplishes what is needed by targets

Hi Everyone！ I am a newbie at llvm. So the question may be fundamental but difficult to me. I want to add an trinsics in x86 and make the following changes.I want that max_qb can find the max of two Integers and return it. In src/include/llvm/IR/Intrinsics.td : let TargetPrefix = "x86" in { def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">,

On Tue, 12 Jul 2005, Aaron Gray wrote: >>>> You shouldn't have to add new classes to the .td file, just modify >>>> printOp for your asmprinters. >>> I dont think printOp is virtual and therefore cannot be overriden ? >> Why does it need to be virtual? No 'intel' printers want % signs. > > The GAS intel code generator generates percents,

>> The GAS intel code generator generates percents, look at the >> X86InstrInfo.td file it is full of them. > > Ah, I see what you're talking about. Please feel free to remove all of > those from the Intel format. For example, change this: > > def IN8rr : I<0xEC, RawFrm, (ops), > "in{b} {%dx, %al|%AL, %DX}">, Imp<[DX],

Hi, I have a custom lowering operation on ISD::BITCAST for the PowerPC/SPE target, to convert 'f64 bitcast (i64 build_pair i32, i32)' into a 'f64 BUILD_SPE64 i32, i32' node, which can be seen at https://reviews.llvm.org/D54583. However, when building compiler-rt's lib/builtins/divdc3.c an assertion is triggered that BUILD_PAIR is not legal on line 24. There should be no

I think that's incorrect. It should to: .section .foo .L1: .L2 = .L1 .section .bar .long .L3-.L2 .L3: Because .L3 and .L2 are in different sections. - Justin On Thu, Jun 26, 2014 at 2:46 PM, Rafael Espíndola <rafael.espindola at gmail.com> wrote: > This reduces to > > .section .foo > .L1: > .L2 = .L1 > .section .bar > .long .L1-.L2 > > > Which is fairly

+ Eli Friedman as he often has very insightful comments regarding back end changes. On Fri, Jan 4, 2019 at 9:03 AM Nemanja Ivanovic <nemanja.i.ibm at gmail.com> wrote: > The changes seem fine to me. I don't think this is excessively intrusive > and it accomplishes what is needed by targets whose call lowering can > introduce illegal types. > Adding Justin Bogner as the

Hello, I'm trying to write assembler code writer, and of course, have new questions. I'd like the structure my implementation like this: if (/*binary instruction*/) { // print destination O << " = "; // print first operand O << opcode; // print second operand. } if (/* unary instruction */ ) { .... } if (/*control instruction*/) { ....

Hi Tim, Tim Northover-2 wrote > The code used for DIV is around X86ISelDAGToDAG.cpp:2415, but from a > glance the key points seem to be: > 1. use the second result of getCopyToReg (i.e. SDValue(setIdNode, 1)) > in the RDMSR node. > 2. Give your RDMSR node type MVT::Glue instead of MVT::Other I tried doing what you said, and the DAG looks like how I think it supposed to look like

I'm working on Position-independent code for 32-bit PowerPC, but running into a problem. At the beginning of each function, there's a pre-word that's the difference between the PICBase (.L1$pb) and the GOT. This works fine when generating assembly output, but it fails when generating ELF output, with the error "Cannot represent a difference across sections" (line 847,

Hi, everyone, I would like to know if anyone is still making use of the support in the PowerPC backend for the IBM BG/Q supercomputer, including the support for its QPX vector instruction set. If you are, please reply. I'm not aware of any still-running BG/Q machines, and if no one is making use of this functionality, I propose that we remove it. Thanks again, Hal Hal Finkel Lead, Compiler

Vladimir Prus wrote: > On my target, the multiplication can involve all general purpose registers, > but there's are still some restrictions: the first and the second operand > as well as the result must be in different registers, and neither register > can be gr7. How can I enforce this restriction on the register allocator? And the other side of the question is now to inform