similar to: Some strange i64 behavior with arm 32bit. (Raspberry Pi)

Hi Tim, thanks for the swift response! @debug is defined in the same module, which makes this all the more confusing. The target information from the working example are: target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv6kz--linux-gnueabihf" from the ghc produced module: target datalayout =

Summary ======= There is a need for dedicated continuation-passing style (CPS) calls in LLVM to support functional languages. Herein I describe the problem and propose a solution. Feedback and/or tips are greatly appreciated, as our goal is to implement these changes so they can be merged into LLVM trunk. Problem ======= Implementations of functional languages like Haskell and ML (e.g., GHC

> Is there a reason you can't use the algorithm from the paper "A Correspondence between Continuation Passing Style and Static Single Assignment Form" to convert your IR to LLVM's SSA IR? Yes, there are a few reasons. Undoing the CPS transformation earlier in the pipeline would mean that we are using LLVM's built-in stack. The special layout and usage of the stack in

> The semantics around inlining alone are problematic enough to warrant serious hesitation. There are nicer ways to embed CPS call/return into LLVM; I just figured that there would not be much support for adding a new terminator because it would change a lot of code. Ideally we would have a block terminator like: cps call ghccc @bar (.. args ..) returnsto label %retpt Where the

> Most architectures have a call instruction which does not push anything onto the stack; e.g. on ARM, the "BL" instruction saves the return address in LR. On other architectures, you can emulate this (for example, you could lower an IR "call" to LEA+JMP on x86-64). This is similar to what I was originally thinking, since the end goal of all of this is the following

(Sorry for the 2nd email Eli, I forgot to reply-all). > I'm not following how explicitly representing the return address of a call in the IR before isel actually solves any relevant issue. We already pass the return address implicitly as an argument to every call; you can retrieve it with llvm.returnaddress if you need it. Unfortunately the @llvm.returnaddress intrinsic does not solve

Hi Moritz, On 26 September 2017 at 09:09, Moritz Angermann via llvm-dev <llvm-dev at lists.llvm.org> wrote: > I’ve run into a case where `llc -mattr=+soft-float` for > "armv7-unknown-linux-androideabi” segfaults, while > `llc -float-abi=soft` does not. Similarly if the > "target-features"="+soft-float” metadata is embedded, > llc segfaults. The float-abi

Hi, I’ve run into a case where `llc -mattr=+soft-float` for "armv7-unknown-linux-androideabi” segfaults, while `llc -float-abi=soft` does not. Similarly if the "target-features"="+soft-float” metadata is embedded, llc segfaults. I fear I’m missing something rather subtle here, could someone help me understand the differences? Cheers, Moritz

> On Mar 14, 2017, at 3:02 AM, Mehdi Amini <mehdi.amini at apple.com> wrote: > >> >> On Mar 11, 2017, at 4:30 PM, Moritz Angermann via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hi Matthias, >> >> what I’m observing right now is that replacing opt+llc with an clang invocation, and >> subsequently fewer intermediate files,

Hi Tim, Ohh, I completely forgot to attach the source. Running this with: $ llc -O2 -mcpu=generic HeapStackCheck.ll -mattr=+soft-float -o HeapStackCheck.s results in 0 llc 0x000000010fea65e6 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 37 1 llc 0x000000010fea5b3a llvm::sys::RunSignalHandlers() + 83 2 llc

Hi *, in the process of improving the ios experience with ghc, I ran into the following issue: the produced llvm code[1] compiles for `armv7-apple-darwin`, unless optimization level is 0, however it fails to compile at all for `armv7-apple-ios`. I was able to reduce the produced code, while retaining the compilation issue on `armv7-apple-ios` to the following sample case: —————————————————————

All, I would like to submit the attached patch, which allows the GHC (Glasgow Haskell Compiler) calling convention to work on ARM targets. Could some nice person please review this code, so I can move towards getting it committed? I have thoroughly tested this patch again GHC on a Debian-ARM (armel) system. Unfortunately my understanding of LLVM is limited, so it's likely I'm not

TL;DR: I'm trying to evaluate if LLD can be used with GHC (Glasgow Haskell Compiler) on Windows. Haskell binary code is usually deployed in "packages". A package typically provides static library(ies) and optionally – shared library(ies) and/or prelinked ('ld -r') object file. The latter is the best way to satisfy GHC runtime linker, since it requires no separate

Hi all, As previously mentioned on this list the Haskell compiler GHC has a new LLVM based back-end. The back-end needs a new calling convention to efficiently use LLVM and that is what this patch does, just for X86 at the moment. Breakdown: 1) Need actual calling convention Touches: - include/llvm/CallingConv.h - lib/Target/X86/X86CallingConv.td 2) Handling new calling

Hi Steve, I'm not an LLVM developer but am the author/maintainer of the LLVM backend in GHC. The patch looks mostly good to me (although I am not that familiar with ARM so could easily have missed something). My main concern is why are you avoiding using the R0 - R3 registers? Also, could you please update me on the status of this work. I assume you are getting GHC running in registerised

Hi all, I'm hitting a segfault in llc when trying to build GHC: http://sprunge.us/ZVGB. What is the best way to debug this? I'm able to bump to 3.8.1 if needed, but GHC tends to break when updating major versions due to IR incompatibilities. Thanks, Shea -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size:

Hi Renato, On 06/25/12 12:13 AM, Renato Golin wrote: > Hi Karel, > > I understand this patch has already been merged (to 3.0), so don't > take my question as stopping the merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9,

On Mon, Dec 16, 2013 at 5:03 AM, Stuart Marsden <stuartmarsden at finmars.co.uk> wrote: > I have just started trying Opus with a view to using it in a project. I am > interested in embedded hardware and tried it on the Raspberry Pi using the > raspbian distro. > > The version of libopus in the repos is 0.9.14. I installed this and tried > encoding 2 minutes of speech from a

Raspberry Pi 1 and Zero use the arm1176jzf-s chip which AFAIK doesn't support NEON intrinsics. This may be a bug with the configure script because it appears to be compiling with NEON enabled. Lifeng can you comment? Is there a way to override the CPU detection in this case? Samuel, as a workaround you can download and compile an older version of the library. I think 1.1.2 predated the NEON

Targetting the raspberry pi, what triple/flags should I set? I tried triple: armv4t-unknown-linux-gnueabi and ld fails with: a.out uses VFP register arguments if i set hardfloat (using optdata.FloatABIType = FloatABI::Hard), ld fails with an assertion: 2.22 assertion fail ../../bfd/elf32-arm.c:11477 what am I missing?