Displaying 14 results from an estimated 14 matches similar to: "Error in generating Object Code for implemented assembly vector instructions"
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
Please tell me whether the following implementation is correct.....
My target supports 64 bit mask means immediate(0-2^63)
I have implemented it but i dont know whether its correct or not. Please
see the changes below that i have made in x86isellowering.cpp
static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int>
Mask,
MVT VT,
2017 Aug 17
2
unable to emit vectorized code in LLVM IR
lli sum-vec03.ll 5 2 #0 0x0000000000c1f818 (lli+0xc1f818)
#1 0x0000000000c1d90e (lli+0xc1d90e)
#2 0x0000000000c1da5c (lli+0xc1da5c)
#3 0x00007f987c2c3d10 __restore_rt
(/lib/x86_64-linux-gnu/libpthread.so.0+0x10d10)
#4 0x00007f987c6f0038
#5 0x0000000000989f8c (lli+0x989f8c)
#6 0x00000000009383dc (lli+0x9383dc)
#7 0x000000000057eedd (lli+0x57eedd)
#8 0x00007f987b464a40 __libc_start_main
2017 Aug 17
2
unable to emit vectorized code in LLVM IR
Ok. I have managed to vectorize the second loop in the following code. But
the first loop is still not vectorized? Why?
int main(int argc, char** argv) {
int a[1000], b[1000], c[1000]; int g=0;
int aa=atoi(argv[1]), bb=atoi(argv[2]);
for (int i=0; i<1000; i++) {
a[i]=aa+i, b[i]=bb+i;}
for (int i=0; i<1000; i++) {
c[i]=a[i] + b[i];
g+=c[i];
}
printf("sum: %d\n", g);
return 0;
2017 Aug 24
2
JIT Optimization Levels
Hello,
there are several optimization levels in lli like O0, O1, O2, O3. What does
they mean? how the run time optimization is performed in LLVM JIT?
I am working on a project where my goal is to study the impact of lli
optimizations. here my IR is already optimized through opt. now i have to
perform lli optimizations provided i am giving varying inputs at run time.
so i suppose here my
2010 Sep 07
1
[LLVMdev] MachineMemOperand and dependence information
Sorry, this is the part in ARMLoadStoreOptimizer.cpp that creates a LDRD
instruction.
Ops.pop_back();
Ops.pop_back();
// Form the pair instruction.
if (isLd) {
MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos,
dl, TII->get(NewOpc))
.addReg(EvenReg, RegState::Define)
2017 Aug 17
3
unable to emit vectorized code in LLVM IR
I want to vectorize the user given inputs. when opt does vectorization user
supplied inputs (from a text file) will be added using AVX vector
instructions.
as you pointed; When i changed my code to following:
int main(int argc, char** argv) {
int a[1000], b[1000], c[1000];
int aa=atoi(argv[1]), bb=atoi(argv[2]);
for (int i=0; i<1000; i++) {
a[i]=aa, b[i]=bb;
c[i]=a[i] + b[i];
2010 Sep 07
0
[LLVMdev] MachineMemOperand and dependence information
On Sep 7, 2010, at 10:48 AM, Akira Hatanaka wrote:
> I have two questions regarding MachineMemOperands and dependence information.
>
> Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
>
> (before optimization)
> %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
2017 Aug 17
4
unable to emit vectorized code in LLVM IR
i removed printf from loop. Now getting no error. but the IR doesnot
contain vectorized code. IR Output is as follows:
; ModuleID = 'sum-vec.ll'
source_filename = "sum-vec.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone uwtable
define i32 @main(i32, i8**
2017 Aug 17
4
unable to emit vectorized code in LLVM IR
I assume compiler knows that your only have 2 input values that you just
added together 1000 times.
Despite the fact that you stored to a[i] and b[i] here, nothing reads them
other than the addition in the same loop iteration. So the compiler easily
removed the a and b arrays. Same with 'c', it's not read outside the loop
so it doesn't need to exist. So the compiler turned your
2010 Sep 07
3
[LLVMdev] MachineMemOperand and dependence information
I have two questions regarding MachineMemOperands and dependence
information.
Q1) I noticed that MachineMemOperands are lost when two LDRs are combined
and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps.
(before optimization)
%reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0;
mem:LD4[%uglygep10]
%reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,
2007 Dec 20
2
[LLVMdev] random warnings
They looked real enough to me:
/Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp: In
function ‘bool<unnamed>::isFPS16Immediate(llvm::ConstantFPSDNode*,
short int&)’:
/Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp:
148: warning: dereferencing type-punned pointer will break strict-
aliasing rules
2017 Aug 17
2
unable to emit vectorized code in LLVM IR
even if i make my code as follows: vectorized instructions not get emitted.
What to do?
int main(int argc, char** argv) {
int a[1000], b[1000], c[1000]; int g=0;
int aa=atoi(argv[1]), bb=atoi(argv[2]);
for (int i=0; i<1000; i++) {
a[i]=aa, b[i]=bb;
c[i]=a[i] + b[i];
g+=c[i];
}
printf("sum: %d\n", g);
return 0;
}
On Thu, Aug 17, 2017 at 10:03 PM, Craig Topper <craig.topper at
2017 Aug 16
2
unable to emit vectorized code in LLVM IR
Hello,
I have written the following code. when i try to vectorize it through opt.
i am not getting vectorized instructions.
#include <stdio.h>
#include<stdlib.h>
int main(int argc, char** argv) {
int sum=0; int a=atoi(argv[1]); int b=atoi(argv[2]);
for (int i=0;i<1000;i++)
{
sum+=a+b;
}
printf("sum: %d\n", sum);
return 0;
}
i use following commands:
clang -S -emit-llvm
2007 Dec 22
0
[LLVMdev] random warnings
On Dec 20, 2007, at 3:56 PM, Mike Stump wrote:
> They looked real enough to me:
Fixed, thanks.
-Chris
>
>
> /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp: In
> function ‘bool<unnamed>::isFPS16Immediate(llvm::ConstantFPSDNode*,
> short int&)’:
> /Volumes/mrs5/net/llvm/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp:
> 148: warning: