similar to: [RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

When we discussed this our line of thought was like this: - LLVM IR already uses %name for SSA values which is closer to what a vreg is than to what a physreg is. It would be neat to draw that parallel to llvm IR. - We wanted another sigil for physregs so they are easy to differentiate from vregs to allow people to differentiate vregs/physregs even if they don't know all the physreg names of

Hi A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs are reserved for vregs. We've decided that to properly implement a syntax for MIR named vregs we first need to reorganized the sigils used for physical registers and external symbols so our proposal is to swap the sigil

On Mon, Jan 8, 2018 at 2:27 PM, Matthias Braun <mbraun at apple.com> wrote: > When we discussed this our line of thought was like this: > > - LLVM IR already uses %name for SSA values which is closer to what a vreg > is than to what a physreg is. It would be neat to draw that parallel to > llvm IR. > - We wanted another sigil for physregs so they are easy to differentiate

Can we use %% for vregs? Seems slightly easier to remember %/%% than $/%. Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. It's all a bikeshed, but being more consistent with assembly is probably a win. -- Sean Silva On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < llvm-dev at

Hi all, Many of us find ourselves spending a great chunk of time comparing LLVM IR dumps at various stages of compilation pipeline or after a given optimization pass. Said process can be extremely laborious, and this is especially true when comparing shaders or compute modules. Important semantic differences are often difficult to spot because of the irregular naming and ordering of instructions.

The MIR format currently has a short-hand syntax for declaring vreg classes and banks in the function body so you can write something like this: name: foo body: | %3:gpr(s64) = ... rather than the much more verbose and awkward: name: foo registers: - { id: 3, class: gpr } body: | %3(s64) = ... I'd like to make this shorthand the only way to do this. There are a few

Is this the configuration you would give for an iphone? -Puyan ----- Original Message ----- From: "Jim Grosbach" <grosbach at apple.com> To: "Puyan Lotfi" <puyan at gatech.edu> Cc: llvmdev at cs.uiuc.edu Sent: Wednesday, February 17, 2010 4:42:37 PM GMT -05:00 US/Canada Eastern Subject: Re: [LLVMdev] Need help getting LLVM JIT running on ARM Specifying --host,

Hi Does there exist a list of relative compile times for source files in LLVM? I am doing a build for ARM on an actual ARM device, and CodeGenDAGPatterns.cpp is taking a really long time to compile (it's been like 20 minutes or more). I don't even get an error. All the files before it compile pretty quickly but this file in particular just won't finish. The version of gcc I have on

Puyan, There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. Rajika On Sun, Feb 21, 2010 at 11:33 AM, Puyan Lotfi <puyan at gatech.edu> wrote: > Hi > > Does there exist a list of relative compile times for source files in LLVM? > I am doing a build for ARM on an actual ARM device, and >

Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? I want to use the LLVM JIT on ARM for a class project this semester. I have built and/or installed a few different gcc arm (arm-linux, and also one that is arm-elf) toolchains, and have had trouble getting LLVM 2.6 to configure and compile using the --host and --build switches of the config. If there

Specifying --host, --build and --target should work. For example, $ configure --host=arm-apple-darwin10 --build=i686-apple-darwin10 --target=arm-apple-darwin10 --enable-targets=arm -Jim On Feb 17, 2010, at 12:26 PM, Puyan Lotfi wrote: > Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? > I want to use the LLVM JIT on ARM for a class

>From a cached version of the Getting Started Guide, I have found: "GCC 3.4.4 (CodeSourcery ARM 2005q3-2): this compiler miscompiles LLVM when building with optimizations enabled. It appears to work with "make ENABLE_OPTIMIZED=1 OPTIMIZE_OPTION=-O1" or build a debug build." I'm trying that now. -Puyan On Sun, Feb 21, 2010 at 1:22 AM, Rajika Kumarasiri <rajika at

Hi, [+ Quentin] Sorry for the late reply. > On Feb 13, 2019, at 9:09 AM, Nikola Prica <nikola.prica at rt-rk.com> wrote: > > On 12.02.2019. 18:06, Adrian Prantl wrote: >> [+ some folks more knowledgable about the Machine layer than me.] >> > That would be useful for us too! :) > > >>> On Feb 12, 2019, at 5:07 AM, Nikola Prica <nikola.prica at

[+ some folks more knowledgable about the Machine layer than me.] > On Feb 12, 2019, at 5:07 AM, Nikola Prica <nikola.prica at rt-rk.com> wrote: > > Hi, > > I am one of the authors of this feature. On Phabricator, we agreed to > take discussion whether encoding this in IR and threading it through the > compiler or performing a late MIR analysis is the better approach.

Hi all, As much as possible I would rather we avoid any kind of metadata in MIR to express the semantic of instructions. Instead I would prefer that each back provides a way to interpret what an instruction is doing. What I have in mind is something that would generalize what we do in the peephole optimizer for instance (look for isRegSequenceLike/getRegSequenceInputs and co.) or what we have for

Hi I am interested to know: are there are any LLVM targets in the works for Nvidia's PTX ISA? Also if anyone knows about Ocelot (a project done by some students at my school): it does the opposite of what I am trying to do (translates PTX to LLVM IR to run Cuda kernels on the CPU). Thanks in advance. -Puyan

Hi debuginfo cabal, tl;dr: I'd like to know what people think about an alternative to DBG_VALUE instructions describing variable locations in registers, virtual or real. Before instruction selection in LLVM-IR we identify the _values_ of variables [0] by the instruction that computes the value; I believe we should be able to do the same post-isel, and it would avoid having to analyse register

Hi I am not sure if it is possible to do something similar to what the LLVM pass framework offers (via the opt program) but in the JIT instead (when running lli). Is it possible to do any kind of online profiling (or optimization) of dynamically compiler code similar to writing an opt style code pass module? Or would I have to change a lot of stuff in the JIT? Thanks -Puyan

On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > Hi > > I am interested to know: are there are any LLVM targets in the works > for Nvidia's PTX ISA? > > Also if anyone knows about Ocelot (a project done by some students at > my school): it does the opposite of what I am trying to do (translates > PTX to LLVM IR to run Cuda kernels on the CPU). I don't know of