similar to: RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends

I agree with David's sentiment. The second method appears to be easier to follow. IMHO, this would be easier for external users that desire to modify the backend for their own custom extensions/instructions. On Fri, Aug 18, 2017 at 5:05 AM, David Chisnall <David.Chisnall at cl.cam.ac.uk > wrote: > On 18 Aug 2017, at 10:55, Alex Bradbury <asb at asbradbury.org> wrote: >

On 21 August 2017 at 11:53, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > One thing to be aware of with this is that (IIRC) tablegen uses the pattern to infer things about the pattern. One example I vaguely remember is that an empty pattern would result in the same effect as hasSideEffects=1 and I think there were others. Thanks for the note - excellent point. Looking at

As you will have seen from previous postings, I've been working on upstream LLVM support for the RISC-V instruction set architecture. The initial RFC <http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html> provides a good overview of my approach. Thanks to funding from a third party, I've recently been able to return to this effort as my main focus. Now feels like a good

What are the correct target description side effect flags for instructions which may trap (e.g. divide / remainder)? The divide instruction in my backend currently has no flags set. I've enabled the MachineLICM pass and it's causing a miscompilation by hoisting a divide by zero instruction out of the loop. Clearly this pass needs to be made aware that this is not safe. The current

> On Mar 21, 2016, at 9:14 PM, Mehdi Amini via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > >> On Mar 21, 2016, at 8:58 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote: >> >> On 19.03.2016 16:25, Mehdi Amini wrote: >>> Hi, >>> >>> Can you elaborate what is the impact at the IR level? >>> If the point is just about

On 19.03.2016 16:25, Mehdi Amini wrote: > Hi, > > Can you elaborate what is the impact at the IR level? > If the point is just about how you lower for you target, why are you needing an IR level attribute? You backend if free to specialize the lowering for any intrinsic regardless the IR level attributes. As I explained in my reply to Philip, what I really need is a way to get

On 15 March 2015 at 16:31, Hal Finkel <hfinkel at anl.gov> wrote: > I don't want to code when to use them. But it makes sense to say, "If you want to include a title tag, do it like this...". I'm ok with that. So, do we have consensus? 1. Don't require, but recommend using [] for tags. 2. Don't specify attribution more than just "patch by Foo." and

On 15 March 2015 at 15:06, Hal Finkel <hfinkel at anl.gov> wrote: > I used to use CSE:, but have now switched to using [CSE] because that seems to be the prevailing convention (and is somewhat more visually distinctive). I think it makes sense to codify that convention, but not to require them. Sometimes, there is nothing appropriate to use. Sometimes, the first or second word of the

On 15 March 2015 at 20:22, Chris Lattner <clattner at apple.com> wrote: > Can you post the entire revised diff that you want to include? Is it Diff 21913 on Phab? If so, LGTM. Hi Chris, Here's the final version: http://reviews.llvm.org/D8197 cheers, --renato

Folks, On review http://reviews.llvm.org/D8197, we're basically down to two bikeshedding issues: 1. Title tags Some people use "[CSE] Change blah", others use "CSE: Change blah". I hadn't put anything regarding tags because not everyone use it and when they do, it's slightly different. I personally don't think it's a reason to argue about, so I'm in

On 14 November 2017 at 16:03, Alex Bradbury <asb at lowrisc.org> wrote: > Dear list, > > At the RISC-V BoF at the LLVM Dev Meeting and the longer working > session the day after, those of us working on RISC-V with LLVM decided > it would be worthwhile to schedule regular sync-up calls in order to > better co-ordinate ongoing work between different developers. This is >

Alex, ping? There was a thread about moving Risc-V out of experimental but I think it didn't go anywhere? Separately, do the listed patches sound okay for merging? Thanks, Hans On Fri, Jan 25, 2019 at 4:40 PM Bruce Hoult <brucehoult at sifive.com> wrote: > > In https://llvm.org/svn/llvm-project/llvm/branches/release_80 I find > that RISCV is still in

Dear list, At the RISC-V BoF at the LLVM Dev Meeting and the longer working session the day after, those of us working on RISC-V with LLVM decided it would be worthwhile to schedule regular sync-up calls in order to better co-ordinate ongoing work between different developers. This is primarily to sync-up, share blocking issues and so on. I understand something similar was done during the

Having worked with a few people to better understand the tablegen descriptions of instructions and patterns in LLVM's backend and looking at x86's pretty heavily, I have some questions: 1) Are there instruction definition flags that are really just "when needed"? I'm thinking of things like "mayLoad" which is really alarmingly missing from a bunch of instructions

Hi, I would like to add a new directive to FileCheck called CHECK-FOO (where FOO is a name under discussion right now) which is used to improve error messages. The idea is that you would use CHECK-FOO on any line that contains a unique identifier (typically labels, function definitions, etc.) that is guaranteed to only occur once in the file; FileCheck will then conceptually break the break the

On 23 November 2017 at 09:38, Alex Bradbury <asb at lowrisc.org> wrote: > On 14 November 2017 at 16:03, Alex Bradbury <asb at lowrisc.org> wrote: >> Dear list, >> >> At the RISC-V BoF at the LLVM Dev Meeting and the longer working >> session the day after, those of us working on RISC-V with LLVM decided >> it would be worthwhile to schedule regular

On Wed, 22 Jan 2020 at 19:55, Chris Lattner via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Jan 21, 2020, at 5:00 AM, Alex Bradbury <asb at lowrisc.org> wrote: > >> This all makes sense to me. > > > > That's correct, thanks for the feedback. > > > > I do like the idea from James of having the compiler always spit out a > > note

Dear testers, 8.0.0-rc1 was just tagged (from the branch at r351980). It took a little longer than planned, but it's looking good. Please run the test script, share your results, and upload binaries. I'll get the source tarballs and docs published as soon as possible, and binaries as they become available. Thanks, Hans

There will be a RISC-V focused Birds of a Feather (BoF) session at the LLVM Dev Meeting in a few weeks time <https://2017llvmdevmtg.sched.com/event/CMiv/co-ordinating-risc-v-development-in-llvm> (Wednesday, October 18, 4:20pm - 5:05pm) The aim of this session is to bring together everyone with an interest in RISC-V support LLVM, and especially those from companies who have had private

Hi all, Some discussions the night before prompted me to do a short lightning talk on 'improving the experience of first-time contributors' at the LLVM Cauldron back in September. I intended to write it up as an RFC, but have only just got round to doing so. I've tried to make this email self-contained, but you may still want to look at the slides or recording of the lightning talk.