similar to: X86PadShortFunction.cpp inserts noops twice

This sounds fine to me (and sorry for the delay!). -- Sanjoy On Mon, Mar 12, 2018 at 1:09 PM, Chawla, Pankaj <pankaj.chawla at intel.com> wrote: > Hi Sanjoy, > > So what is the verdict on this issue? > > Thanks, > Pankaj > > > -----Original Message----- > From: Chawla, Pankaj > Sent: Monday, February 26, 2018 11:12 AM > To: Sanjoy Das <sanjoy at

Hi Pankaj, On Tue, Mar 13, 2018 at 1:55 PM, Chawla, Pankaj <pankaj.chawla at intel.com> wrote: > Thanks for the reply! > Would it be possible for you to implement this? I don't have cycles for this right now, but if you file a bug I can give this a shot when I have time later. Even in the best case this will have to at least wait until end of April because I'm leaving for a

Hi Sanjoy, Thanks for the reply! Would it be possible for you to implement this? You know the codebase better than I do. Thanks, Pankaj -----Original Message----- From: Sanjoy Das [mailto:sanjoy at playingwithpointers.com] Sent: Tuesday, March 13, 2018 1:34 PM To: Chawla, Pankaj <pankaj.chawla at intel.com> Cc: Maxim Kazantsev <max.kazantsev at azul.com>; Serguei Katkov

Hi All, The landed patch https://reviews.llvm.org/D38481 introduced the usage of CPU_COUNT defined in glibc sched.h header. I failed to find this symbol in sched.h of glibc version 2.5-24, so compilation just fails. /home/dolphin/merge-from-upstream-area/ws/pristine/lib/Support/Threading.cpp: In function 'unsigned int llvm::hardware_concurrency()':

Hi Sanjoy, >> I'm a bit apprehensive of adding more caching to solve problems created by caching; but if there is no way out of adding another cache, how about adding a cache that maps SCEV expressions to their simplified versions? Then we could do something like: I may be wrong but I think caching is not an issue in itself, but caching in the presence of self-recursion is. >>

Hi Sanjoy, So what is the verdict on this issue? Thanks, Pankaj -----Original Message----- From: Chawla, Pankaj Sent: Monday, February 26, 2018 11:12 AM To: Sanjoy Das <sanjoy at playingwithpointers.com> Cc: Maxim Kazantsev <max.kazantsev at azul.com>; Serguei Katkov <serguei.katkov at azul.com>; llvm-dev at lists.llvm.org Subject: RE: [SCEV] Inconsistent SCEV formation for

Reverted: https://reviews.llvm.org/rL314922 On Oct 4, 2017, at 1:17 PM, Philip Reames via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: + Rui, the patch author Do we know what the oldest glibc which works with this patch is? For context, the most recent REHL 5 ships with glibc 2.5. REHL 6 ships with 2.12 and REHL ships with 2.17. I have evidence

ðÏÞÅÍÕ ÂÙ É ÎÅÔ? ÷ÏÐÒÏÓ ÔÏÌØËÏ × ÔÏÍ, ËÁË Õ ÔÅÂÑ ÂÕÄÅÔ ÓÏÅÄÉÎÑÔØÓÑ ÐÁÎÁÓÏÎÉË Ó ÁÓÔÅÒÉÓËÏÍ. Date: Wed, 30 Jul 2003 20:06:17 +0400 From: Pavel Zheltouhov <pavlo@comlink.ru> To: asterisk-users@lists.digium.com Subject: [Asterisk-Users] asterisk,ata186 and Panasonic TD1232 Reply-To: asterisk-users@lists.digium.com I have Panasonic TD1232 pbx, few cisco ata186 and linux box with asterisk.

Hi All, I was surprised to notice that a call to noop from puppetrun did not work as expected. on the agent side (for this case the server side..), I ran: puppetd --verbose --no-daemonize (where listen is set in the puppet.conf) on the puppet server side(in this case the client side), I ran: puppetrun --noop --host SERVER notice: SERVER(IP) triggered run info: Caching catalog at

Hi, +CC Max, Serguei This looks like a textbook case of why caching is hard. We first call getZeroExtendExpr on %dec, and this call does end up returning an add rec. However, in the process of simplifying the zext, it also calls into isLoopBackedgeGuardedByCond which in turn calls getZeroExtendExpr(%dec) again. However, this second (recursive) time, we don't simplify the zext and cache a

Our build system is setup to deliberately use a very old environment.  We've found that's one of the most reliable easy ways to ensure we don't accidentally introduce a dependency on a newer system library than intended.  This lets us ship prebuilt binaries which run on a wide spectrum of systems.  We're going to chat internally and check to see if we can roll this forward a

Hi Sanjoy, SCEV is behaving inconsistently when forming SCEV for this zext instruction in the attached test case- %conv5 = zext i32 %dec to i64 If we request a SCEV for the instruction, it returns- (zext i32 {{-1,+,1}<nw><%for.body>,+,-1}<nw><%for.body7> to i64) This can be seen by invoking- $ opt -analyze -scalar-evolution inconsistent-scev-zext.ll But when computing

Dear Community, I'm trying to implement optimization described in PR26223 and meet the following bail out condition in CodeGenPrepare::optimizeMemoryInst. // Break use-def graph loops. if (!Visited.insert(V).second) { Consensus = nullptr; break; } So while traversing thorough phi nodes from memory instruction to find addr mode we bail out if we meet some instruction

Hello All, I filed a bug https://bugs.llvm.org/show_bug.cgi?id=35884 which I want to fix but I'm in trouble with detecting who is wrong :) The story is as follows: LoopDeletion tries to delete an invariant loop which has a def with use in some unreachable block. The IR is well-formed due to any use in unreachable block is dominated as Verifier states. LoopDeletion detected the loop as

On Oct 4, 2017 2:31 PM, "Rui Ueyama via llvm-dev" <llvm-dev at lists.llvm.org> wrote: On Wed, Oct 4, 2017 at 2:19 PM, Philip Reames <listmail at philipreames.com> wrote: > Our build system is setup to deliberately use a very old environment. > We've found that's one of the most reliable easy ways to ensure we don't > accidentally introduce a dependency

I have an ATA-186 in a SIP configuration (following Shawn Djernes how-to), but I get the following error at the asterisk console when I try to call the phone connected to the ATA: ioctl(ZT_LOADZONE) failed: Inappropriate ioctl for device Failed to register zone 'United States / North America': No data available Everything works if I remove indications.conf from /etc/asterisk -

Hi Sanjoy, Thanks for investigating the issue! I am more interested in getting the underlying problem fixed rather than making this particular test case work. I think I have more test cases where this problem crops up. I would any day prefer consistent results over compile time savings which can lead to inconsistencies. These inconsistencies require significant developer time to analyze and fix

Hello, find enclosed a first patch for adding tail call optimizations for thumb1 targets. I assume that this list is the right place for publishing patches for review? Since this is my first proposal for LLVM, I'd very much appreciate your feedback. What the patch is meant to do: For Tail calls identified during DAG generation, the target address will be loaded into a register by use

Hi, This code loops through my results and saves them : @results.each{|r| r.save} There are potentially thousands of results. This takes ages to complete. Is there a quicker way to do this? Any help is greately appreciated Thanks Chris -- Posted via http://www.ruby-forum.com/.

Hello, ive set up file column like so Controller: def entry @entry = Entry.new(@params[:entry]) if @entry.save flash[:notice] = ''Product was successfully updated.'' else flash[:notice] = ''?'' end end Model: file_column :image View: <%= form_tag({:action=>''entry'', :id=> @entry