similar to: CHAINing to a USB Thumb Drive

Just tried the latest release and found a minor bug. Have a UFD w/ SYSLINUX, which boots a simple .BSS image no problem. Launching exactly the same image on a ISOLINUX disc fails w/ the following error msg: Invalid image type for this media That's it for this msg. Later....Jet -- Powered by Outblaze

My compliments on the release of syslinux-5.0 and happy holidays to the entire Syslinux team.? I have a longer message in me.? Lots of curiousity about the direction of the project, but that will have to wait until I finish my first 5.0 project (*not* my first Syslinux project), which just happens to touch past problems: drive enumeration. This particular effort is on a USB flash drive, with two

Hi, I wanted to know if it was possible to force ARM backend to compile a function in ARM while the rest is in Thumb mode. I tried the attributes which is used in GCC but it doesn't work. Here is what I tried: https://pastebin.com/jCr5LPUY Thanks in advance, Uvekilledkenny -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, We are trying to use clang as a drop-in replacement for the gcc come with Android NDK. I found that MC/ELF doesn't not handle Thumb functions properly, e.g., bit 0 of the function name in the .symtab is not set to 1, and some thumb instructions are not generated correctly, e.g., the addresses for tBL/tBLX are not calculated right. With that attached patch, we can compile and run some

Hi Koan, In general, this looks OK to me. Please split the patch into separate pieces, one for each issue you're addressing, though. From your description, it sounds like this should be 4 patches. That way we have a cleaner revision history in svn. -Jim On May 12, 2011, at 10:42 PM, Koan-Sin Tan wrote: > Hi, > > We are trying to use clang as a drop-in replacement for the gcc come

Hi I would like to use clang to cross compile the ARM binary. I hope the target binary contains both arm and thumb instruction sets. I use the flag -mhwdiv=arm,thumb. I compiled several binaries. However, I found that the thumb mode instructions are few. Even for very big program like gcc. The number of thumb mode instruction is less than 100. I get the ground truth from the mapping table.

Hello: New to linux, and Centos. Can I plug thumb drive into computer, and download Centos directly to thumb drive, then move thumb drive to another desktop and use it like a "live CD" to install it on that computer? Thanks for any help. Tom

Dear list, I have a problem with freq from prettyR. Please have a look at my syntax with a litte example: library(prettyR) #Version 1 test.df<-data.frame(q1=sample(1:4,8,TRUE), gender=sample(c("f","m"),8,TRUE)) test.df freq(test.df) #No error message #Version 2 test.df<-data.frame(gender=sample(c("f","m"),8,TRUE), q1=sample(1:4,8,TRUE)) test.df

Hi everyone, I'm working on some custom transformation passes that have the side-effect of significantly increasing the code size. While testing it on some larger, real-world code bases, I run into a linker error for armv7 thumb code. The particular error I get from ld64 is that "armv7 has no pc-rel bx thumb instruction." I've been able to reproduce the problem by taking a

Hi, I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. Here is output: # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) Target: arm-unknown-freebsd Thread

Hi all, When I use Clang, I can add -mno-thumb to the command line and Clang generates pure Arm code without any use of Thumb instructions. However, I am messing about with the Glasgow Haskell Compiler (GHC) which generates LLVM IR code directly and then calls `opt` and `llc` on that IR code. The generated IR code currently has: target datalayout =

Hello everyone, I want to generate machine code for target thumb, so run with bit code test.bc llc -march thumb test.bc -filetype obj -o test.o It doesn't generate test.o but show a message: "target doesn't support generation of this file type!" What's wrong? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi Nowadays I am using LLVM to do ARM binary analysis. I was wondering is llvm available to provide some debugging information on the mode of ARM. For example, llvm-dwarfdump could dump some instructions information for debugging. Is it able to know the mode for each instruction? Or we may write some llvm pass to help us to know the instruction mode? Any suggestions are welcomed. Many Thanks

Hi all, I'm trying to figure out a problem with relocation types 1 and 8 (as observed using otool -r on ARM/Thumb object files). Earlier, when I used LLVM 2.8 with llc to generate thumb (-march=thumb -mattr=+thumb2) assembly listings, then assemble those using the gcc of iPhone 4.2 SDK, there wasn't any problem. However starting with LLVM 2.9, the same toolchain emits slightly different

Hi > I just realized that clang produces Thumb-2 instruction in code even when older CPU type which doesn't suport Thumb-2 is specified. > > Here is output: > > # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c > clang version 3.0 (http://llvm.org/git/clang.git 98138cdfdee05c0afbab2b209ce8cfe4a52474e1) >

I see strangeness on Thumb TST (tTST) predicate 'isCompare' It is true for regular ARM, false for Thumb: (gdb) p MI->dump() TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR<imp-def>; GPR:% reg16397 $24 = void (gdb) p MI->getDesc().isCompare() $25 = true (gdb) p MI->dump() tTST %reg16396, %reg16397, pred:14, pred:%reg0, %CPSR<imp-def>; tGPR:%reg16396,16397

On 22 June 2011 11:49, Damjan Marion <damjan.marion at gmail.com> wrote: > # /opt/llvm/bin/clang -S -ccc-host-triple arm-unknown-freebsd -mcpu=arm926ej-s -mfloat-abi=soft -v -o rrx.S rrx.c Even though you specified cpu as arm9, it's probably generating generic ARM IR (use -emit-llvm -S and see), which defaults to ARM instructions. If you want thumb, use triple =

The llvm compiler can now generated movt/movw instructions to create 32-bit constants. Those new instructions use new relocations. Mach-o uses different numbering for relocations than ELF does. For mach-o, ARM_RELOC_PAIR=1 and ARM_RELOC_HALF=8. You need a newer linker that understands the new relocations. -Nick On Feb 20, 2012, at 5:20 AM, Harel Cain wrote: > Hi all, > > I'm

Tim Northover wrote: > That shouldn't be happening. The "armv6" ought to imply ARM mode. What > Thumb instructions are you seeing, and do you have a .ll file that > reproduces the issue with standard tools or is it just the way GHC is > driving LLVM? Sorry false alarm. I was a looking an object file produced by GCC compiling a C file, not an object file produced by GHC

Thanks, Shankar. I needed to override all the places where st_value had been used, and it worked. But there another problem appeared: after correcting all atoms, I cannot distinguish between ARM and Thumb symbols in the further stages when fixing up relocations. I used to check targetVAddress (in terms of the relocation handler) since it contained 1 in the least bit when addressing Thumb