similar to: [PATCH] VMX: wbinvd when vmentry under UC

Displaying 20 results from an estimated 1000 matches similar to: "[PATCH] VMX: wbinvd when vmentry under UC"

2013 Oct 30
3
[PATCH 4/4] XSA-60 security hole: flush cache when vmentry back to UC guest
From 159251a04afcdcd8ca08e9f2bdfae279b2aa5471 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Thu, 31 Oct 2013 06:38:15 +0800 Subject: [PATCH 4/4] XSA-60 security hole: flush cache when vmentry back to UC guest This patch flush cache when vmentry back to UC guest, to prevent cache polluted by hypervisor access guest memory during UC mode. The elegant way to do this
2008 Sep 09
9
[PATCH 2/4] CPUIDLE: Avoid remnant LAPIC timer intr while force hpetbroadcast
CPUIDLE: Avoid remnant LAPIC timer intr while force hpetbroadcast LAPIC will stop during C3, and resume to work after exit from C3. Considering below case: The LAPIC timer was programmed to expire after 1000us, but CPU enter C3 after 100us and exit C3 at 9xxus. 0us: reprogram_timer(1000us) 100us: entry C3, LAPIC timer stop 9xxus: exit C3 due to unexpected event, LAPIC timer continue running
2012 Mar 01
3
[PATCH v2] x86: Use deep C states for off-lined CPUs
# HG changeset patch # User Boris Ostrovsky <boris.ostrovsky@amd.com> # Date 1330642361 -3600 # Node ID 99df5c6b2964ceaa73651d7bc02fb1ae820f7691 # Parent a7bacdc5449a2f7bb9c35b2a1334b463fe9f29a9 x86: Use deep C states for off-lined CPUs Currently when a core is taken off-line it is placed in C1 state (unless MONITOR/MWAIT is used). This patch allows a core to go to deeper C states
2017 Oct 04
0
[PATCH 01/13] x86/paravirt: remove wbinvd() paravirt interface
Since lguest was removed, only the native version of wbinvd() is used. The paravirt interface is no longer needed. Signed-off-by: Josh Poimboeuf <jpoimboe at redhat.com> --- arch/x86/include/asm/paravirt.h | 5 ----- arch/x86/include/asm/paravirt_types.h | 1 - arch/x86/include/asm/special_insns.h | 7 +------ arch/x86/kernel/paravirt.c | 1 -
2005 Sep 27
0
[PATCH][VT] add "wbinvd" instruction emulattion for real mode code
This patch adds "wbinvd" instruction emulation for vm86 mode. This is needed when we bring up AP of SMP VMX guest. Signed-off-by: Xin Li <xin.b.li@intel.com> diff -r 94c6fc048d8e tools/firmware/vmxassist/vm86.c --- a/tools/firmware/vmxassist/vm86.c Fri Sep 23 11:52:43 2005 +++ b/tools/firmware/vmxassist/vm86.c Tue Sep 27 17:17:25 2005 @@ -752,6 +752,9 @@
2017 Oct 24
0
[PATCH 01/13] x86/paravirt: remove wbinvd() paravirt interface
On 04/10/17 17:58, Josh Poimboeuf wrote: > Since lguest was removed, only the native version of wbinvd() is used. > The paravirt interface is no longer needed. > > Signed-off-by: Josh Poimboeuf <jpoimboe at redhat.com> Reviewed-by: Juergen Gross <jgross at suse.com> Juergen
2010 Aug 18
4
RE: [PATCH 05/15] Nested Virtualization: core
> + > +/* The exitcode is in native SVM/VMX format. The forced exitcode > + * is in generic format. > + */ Introducing a 3rd format of exitcode is over-complicated IMO. > +enum nestedhvm_vmexits > +nestedhvm_vcpu_vmexit(struct vcpu *v, struct cpu_user_regs *regs, > + uint64_t exitcode) > +{ I doubt about the necessary of this kind of wrapper. In single layer
2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch
2017 Sep 25
10
[PATCH v1 0/4] Enable LBR for the guest
This patch series enables the Last Branch Recording feature for the guest. Instead of trapping each LBR stack MSR access, the MSRs are passthroughed to the guest. Those MSRs are switched (i.e. load and saved) on VMExit and VMEntry. Test: Try "perf record -b ./test_program" on guest. Wei Wang (4): KVM/vmx: re-write the msr auto switch feature KVM/vmx: auto switch
2008 Mar 14
4
[PATCH] vmx: fix debugctl handling
I recently realized that the original way of dealing with the DebugCtl MSR on VMX failed to make use of the dedicated guest VMCS field. This is being fixed with this patch. What is puzzling me to a certain degree is that while there is a guest VMCS field for this MSR, there''s no equivalent host load field, but there''s also no indication that the MSR would be cleared during a
2020 Oct 20
5
write.csv covert Åland to <c5>land
Hi there, I tried to export the names of country to a csv file with write.csv(). In the resulted file, ?land was coverted to <c5>land. Is there any way could prevent this happening? Thanks! > abc [1] "?land" > write.table(abc, file = "") "x" "1" "<c5>land" Best, Jinsong
2010 Jun 29
5
More than two font in a plot
Hi there, I am a Chinese R user. I hope to display Chinese character in a plot, and than save it in PostScript format. I have read the article titled "Non-Standard Fonts in PostScript and PDF Graphics", especially the section about CJK fonts. I also tried the code: > pdf("chinese.pdf", width=3, height=1) > grid.text("\u4F60\u597D", y=2/3,
2012 Jun 27
18
[xen vMCE RFC V0.2] xen vMCE design
Hi, This is updated xen vMCE design foils, according to comments from community recently. This foils focus on vMCE part of Xen MCA, so as Keir said, it''s some dense. Later Will will present a document to elaborate more, including Intel MCA and surrounding features and Xen implementation. Thanks, Jinsong
2012 Sep 20
4
[PATCH 0/3] tsc adjust implementation for hvm
Intel recently release a new tsc adjust feature at latest SDM 17.13.3. CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. Basically it is used to simplify TSC synchronization, operation of IA32_TSC_ADJUST MSR is as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the
2010 Aug 07
10
[PATCH] Fix hvm vcpu hotplug bug
When hotplug hvm vcpu by ''xm vcpu-set'' command, if it add/remove many vcpus by 1 ''xm vcpu-set'' command, it has a bug that it cannot add/remove all vcpus that want to be added/removed. This patch is to fix the bug. It delays trigger sci until all xenstore cpu node status are watched. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
2009 Jan 22
2
[PATCH 4/4] X86 microcode: add S3 micorcode update
X86 microcode: add S3 micorcode update When wakeup from S3, use per cpu microcode image to update cpu microcode. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
2013 Apr 09
39
[PATCH 0/4] Add posted interrupt supporting
From: Yang Zhang <yang.z.zhang@Intel.com> The follwoing patches are adding the Posted Interrupt supporting to Xen: Posted Interrupt allows vAPIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu. Then the vcpu will handle this
2020 Oct 20
0
write.csv covert Åland to <c5>land
Hi there, Why the same string is displayed in different form? > abc[,1] [1] "?land" "Afghanistan" > abc name 1 <c5>land 2 Afghanistan And more... > dput(abc, "aa.txt") > dget("aa.txt") name 1 <c5>land 2 Afghanistan > dget("aa.txt")[,1] [1] "<c5>land"
2004 Aug 03
4
How to select a whole column? Thanks!
Dear all, I hope to remove a whole column from a data frame or matrix (> 2000 columns). All value in the column are same. The first thing is to select those columns. For instance, I hope to remove the V3~6 column, for all the value in those colume is zero. V3 V4 V5 V6 V7 V8 V9 V10 1 0 0 0 0 0.000 0.000 0.000 0.000 2 0 0 0 0 0.000 0.000 0.000 0.000 3 0 0 0
2012 Feb 23
7
[PATCH 2/2] RFC: Xen pad logic
From ba9abf6ee7e5fe0515e2d51b14743c8d5416285c Mon Sep 17 00:00:00 2001 From: Liu, Jinsong <jinsong.liu@intel.com> Date: Fri, 24 Feb 2012 02:18:02 +0800 Subject: [PATCH 2/2] Xen pad logic This patch implement Xen pad logic, and when getting pad device notification, it hypercalls to Xen hypervisor for core parking. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> ---