similar to: [PATCH] Nested VMX: Expose unrestricted guest feature to guest

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

The previous order of relinquish resource is: relinquish_domain_resources() -> vcpu_destroy() -> nvmx_vcpu_destroy(). However some L1 resources like nv_vvmcx and io_bitmaps are free in nvmx_vcpu_destroy(), therefore the relinquish_domain_resources() will not reduce the refcnt of the domain to 0, therefore the latter vcpu release functions will not be called. To fix this issue, we need to

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

Changes from v1 to v2: - Use a macro to replace the hardcode in patch 1/3. This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page

TPR shadow/threshold feature is important to speedup the boot time for Windows guest. Besides, it is a must feature for certain VMM. We map virtual APIC page address and TPR threshold from L1 VMCS, and synch it into shadow VMCS in virtual vmentry. If TPR_BELOW_THRESHOLD VM exit is triggered by L2 guest, we inject it into L1 VMM for handling. Besides, this commit fixes an issue for apic access

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

Otherwise we may leak memory when setting up nHVM fails half way. This implies that the individual destroy functions will have to remain capable (in the VMX case they first need to be made so, following 26486:7648ef657fe7 and 26489:83a3fa9c8434) of being called for a vCPU that the corresponding init function was never run on. Once at it, also remove a redundant check from the corresponding

Direct calls perform better, so we should prefer them and use indirect ones only when there indeed is a need for indirection. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -1373,7 +1373,7 @@ void error_interrupt(struct cpu_user_reg void pmu_apic_interrupt(struct cpu_user_regs *regs) { ack_APIC_irq(); -

while doing "while xm migrate --live domU localhost;do sleep 1;done" I just got the crash shown below. And it can be reproduced. The guest has 2 vcpus and 512mb, it runs pvops 3.7.9 (XEN) ----[ Xen-4.3.26579-20130219.172714 x86_64 debug=n Not tainted ]---- (XEN) CPU: 14 (XEN) RIP: e008:[<ffff82c4c01dd197>] nvmx_vcpu_destroy+0xb7/0x150 (XEN) RFLAGS: 0000000000010282

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

From eb20603913ff7350cd25b39d1eb37b8fddd16053 Mon Sep 17 00:00:00 2001 From: Zhang Xiantao <xiantao.zhang@intel.com> Date: Sat, 25 Aug 2012 04:11:08 +0800 Subject: [PATCH 2/2] Nested: VM_ENTRY_IA32E_MODE shouldn''t be in default1 class for IA32_VM_ENTRY_CTLS_MSR. If set to 1, L2 guest''s paging mode maybe mis-judged and mis-set. Signed-off-by: Zhang Xiantao

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

From: Yang Zhang <yang.z.zhang@Intel.com> We exposed the xsave feature to guest, but we didn''t allow guest to set CR4.OSXSAVE when guest running in nested mode. This will cause win 7 guest fail to use XP mode. In this patch, we allow guest to set CR4.OSXSAVE in nested mode when it has the xsave feature. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> ---

The first and third patches are cleaned up versions of an earlier v3 submission by Yang. 1: Nested VMX: check VMX capability before read VMX related MSRs 2: VMX: clean up capability checks 3: Nested VMX: fix IA32_VMX_CR4_FIXED1 msr emulation 4: x86: make hvm_cpuid() tolerate NULL pointers Signed-off-by: Jan Beulich <jbeulich@suse.com>

Dear All, My question is: how can I estimate VECM system with "unrestricted trend" (aka "case 5") option as a deterministic term? As far as I know, ca.jo in urca package allows for "restricted trend" only [vecm <- ca.jo(data, type = "trace"/"eigen", ecdet = "trend", K = n, spec = "transitory"/"longrun")].

X86: implement PCID/INVPCID for hvm This patch handle PCID/INVPCID for hvm: For hap hvm, we enable PCID/INVPCID, since no need to intercept INVPCID, and we just set INVPCID non-root behavior as running natively; For shadow hvm, we disable PCID/INVPCID, otherwise we need to emulate INVPCID at vmm by setting INVPCID non-root behavior as vmexit. Signed-off-by: Liu, Jinsong

The aim of this patch is to define a stable way in which PVH is going to do AP bringup. Since we are running inside of a HVM container, PVH should only need to set flags, cr3 and user_regs in order to bring up a vCPU, the rest can be set once the vCPU is started using the bare metal methods. Additionally, the guest can also set cr0 and cr4, and those values will be appended to the default values

This is a patch repairing a regression in code previously functional in 4.1.x. It appears that, during some refactoring work, calls to hvm_memory_event_cr3 and hvm_memory_event_cr4 were lost. These functions were originally called in mov_to_cr() of vmx.c, but the commit http://xenbits.xen.org/hg/xen-unstable.hg/rev/1276926e3795 abstracted the original code into generic functions up a level in

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

This patch series tidies up a few bits ofthe nested p2m code. The main thing it does is reorganize the locking so that most of the changes to nested p2m tables happen only under the p2m lock, and the nestedp2m lock is only needed to reassign p2m tables to new cr3 values. Changes since v1: - a few minor fixes - more sensible flushing policy in p2m_get_nestedp2m() - smoke-tested this time!