similar to: [PATCH 2/3 v3] Refactor MSI restore call-chain to drop unnecessary argument

Displaying 20 results from an estimated 300 matches similar to: "[PATCH 2/3 v3] Refactor MSI restore call-chain to drop unnecessary argument"

2014 Aug 20
1
[RFC PATCH 10/11] PCI/MSI: Split the generic MSI code into new file
> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at
2014 Aug 20
1
[RFC PATCH 10/11] PCI/MSI: Split the generic MSI code into new file
> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at
2014 Jul 26
20
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use
2014 Jul 26
20
[RFC PATCH 00/11] Refactor MSI to support Non-PCI device
Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use
2014 Aug 20
1
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at
2014 Aug 20
1
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at
2014 Jul 26
0
[RFC PATCH 10/11] PCI/MSI: Split the generic MSI code into new file
MSI interrupt will not only used in PCI device, more and more Non-PCI device also want to use MSI. ARM GIC v3 spec says in ARM platform with GIC v3 controller, Non-PCI device can also be design to support MSI to simplify interrupt wires, for the existing Non-PCI device, consolidator is designed and used to translate legacy interrupt to MSI. So for support Non-PCI MSI device, generic MSI driver is
2014 Jul 26
0
[RFC PATCH 09/11] PCI/MSI: refactor PCI MSI driver
Use struct msi_ops to hook PCI MSI operations, and use struct msi_irqs to refactor PCI MSI drvier. Signed-off-by: Yijing Wang <wangyijing at huawei.com> --- drivers/pci/msi.c | 351 ++++++++++++++++++++++++++++++--------------------- include/linux/msi.h | 14 +- include/linux/pci.h | 11 +- 3 files changed, 222 insertions(+), 154 deletions(-) diff --git a/drivers/pci/msi.c
2011 Sep 20
0
[PATCH 4/4] x86: split MSI IRQ chip
With the .end() accessor having become optional and noting that several of the accessors'' behavior really depends on the result of msi_maskable_irq(), the splits the MSI IRQ chip type into two - one for the maskable ones, and the other for the (MSI only) non-maskable ones. At once the implementation of those methods gets moved from io_apic.c to msi.c. Signed-off-by: Jan Beulich
2014 Aug 20
1
[RFC PATCH 11/11] x86/MSI: Refactor x86 MSI code
> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at
2014 Aug 20
1
[RFC PATCH 11/11] x86/MSI: Refactor x86 MSI code
> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at
2013 May 08
11
[PATCH 1/2] xen, libxc: init msix addr/data with value from qemu via hypercall
Accelerated msix entry is initialized to zero when msixtbl_pt_register is called. This doesn''t match the value from qemu side, although pirq may already be mapped and binded in qemu side. Kernel will get wrong value when reading msix info. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@oracle.com> Tested-by: Yuval Shaia <yuval.shaia@oracle.com> --- tools/libxc/xc_domain.c
2012 Jan 12
9
Re: [PATCH] add netconsole support for xen-netfront
On Wed, Jan 11, 2012 at 04:52:36PM +0800, Zhenzhong Duan wrote: > add polling interface to xen-netfront device to support netconsole > Ian, any thoughts on the spinlock changes? > Signed-off-by: Tina.Yang <tina.yang@oracle.com> > Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> > Cc: Jeremy Fitzhardinge <jeremy@goop.org> > Signed-off-by: Zhenzhong.Duan
2013 Feb 26
4
passthroughed msix device
Hi maintainer, Reprodue an bug on xen-unstable, it''s an irq affinity issue for passthroughed msix device to uek1 pvhvm(2.6.32 stable). I passthrough two mptsas devices(0000:0d:0.0, 0000:1f:0.0) to a pvhvm, irq affinity can''t be changed. Step to reproduce is as below: 1. xl -f pci-assignable-add 0000:0d:0.0; xl -f pci-assignable-add 0000:1f:0.0 2.xm cr -c vm.cfg
2012 Jul 04
3
[PATCH] xen: populate correct number of pages when across mem boundary
When populate pages across a mem boundary at bootup, the page count populated isn't correct. This is due to mem populated to non-mem region and ignored. Pfn range is also wrongly aligned when mem boundary isn't page aligned. Also need consider the rare case when xen_do_chunk fail(populate). For a dom0 booted with dom_mem=3368952K(0xcd9ff000-4k) dmesg diff is: [ 0.000000] Freeing
2012 Jul 04
3
[PATCH] xen: populate correct number of pages when across mem boundary
When populate pages across a mem boundary at bootup, the page count populated isn't correct. This is due to mem populated to non-mem region and ignored. Pfn range is also wrongly aligned when mem boundary isn't page aligned. Also need consider the rare case when xen_do_chunk fail(populate). For a dom0 booted with dom_mem=3368952K(0xcd9ff000-4k) dmesg diff is: [ 0.000000] Freeing
2010 Dec 26
3
How to debug driver code when app run on wine?
I am trying to debug opengl driver when windows Direct3D game runs on wine, and encounter the problem Working on SUSE 11.2, and download the wine binary by YaST2, then: root>gdb wine gdb> b driver_init gdb> r game.exe then I can break the driver on driver_init, and i can see the driver stack by bt, but I cannot see the driver source code, debugger can not find the source code file, but
2014 Jul 04
2
How to check for proper MSI support?
On Thu, Jul 3, 2014 at 11:09 PM, Yijing Wang <wangyijing at huawei.com> wrote: > On 2014/7/4 10:43, Ilia Mirkin wrote: >> On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang <wangyijing at huawei.com> wrote: >>> Hi Brian, >>> From your 01:00.0 VGA compatible controller PCI config register, it supports 1 MSI vector, so I think this >>> card has no
2012 Oct 18
3
ask a question about ERST
Hi maintainer, I found below patch reverted part of erst header size check. This lead to mismatch with kernel upstream code and erst disabled on some machine like X4170 M3/X3-2. According to the ACPI spec 4.0 and 5.0, the Serialization Header Length should be the length of Serialization Header. After revert below patch, xen succeed with erst table init. So could this patch be reverted now to match
2013 Aug 30
3
[PATCH v7] interrupts: allow guest to set/clear MSI-X mask bit
Guest needs the ability to enable and disable MSI-X interrupts by setting the MSI-X control bit, for a passed-through device. Guest is allowed to write MSI-X mask bit only if Xen *thinks* that mask is clear (interrupts enabled). If the mask is set by Xen (interrupts disabled), writes to mask bit by the guest is ignored. Currently, a write to MSI-X mask bit by the guest is silently ignored. A