similar to: [PATCH] xen/arm: Dummy implementation of multi-bank support

Displaying 15 results from an estimated 15 matches similar to: "[PATCH] xen/arm: Dummy implementation of multi-bank support"

2012 Mar 15
3
[PATCH] arm: allocate top level p2m page for all non-idle VCPUs
Not just dom0. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- xen/arch/arm/domain.c | 3 +++ xen/arch/arm/domain_build.c | 3 --- xen/arch/arm/p2m.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 5702399..4b38790 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@
2012 Mar 19
24
[PATCHv2 00/11] arm: pass a device tree to dom0
This series of patches makes Xen pass a (somewhat) valid device tree to dom0. The device tree for dom0 is the same as the one supplied to Xen except the memory and chosen nodes are adjusted appropriately. We don''t yet make use of the device tree to map MMIO regions or setup interrupts for the guest and we still include the UART used for Xen''s console. Note that loading Linux
2012 Nov 30
1
[PATCH v2] arm: add few checks to gic_init
Check for: - uninitialized GIC interface addresses; - non-page aligned GIC interface addresses. Panic in both cases. Also remove the code from GICH and GICC to handle non-page aligned interfaces. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 8efbeb3..2b29e7e 100644 --- a/xen/arch/arm/gic.c +++
2013 Mar 14
1
[PATCH] x86/mce: Use MCG_CAP MSR to find out number of banks on AMD
Currently number of error reporting register banks is hardcoded to 6 on AMD processors. This may break in virtualized scenarios when a hypervisor prefers to report fewer banks that the physical HW provides. Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0] that''s what we should use. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> ---
2013 Mar 14
0
[PATCH v2 2/2] x86/mce: Use MCG_CAP MSR to find out number of banks on AMD
Currently number of error reporting register banks is hardcoded to 6 on AMD processors. This may break in virtualized scenarios when a hypervisor prefers to report fewer banks than what the physical HW provides. Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0] that''s what we should use. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> ---
2006 Jan 16
13
Support for AGP aperture as IOMMU in AMD64 mode [2/2]
These are the diffs against the pristine versions of arch/x86_64/kernel/[aperture.c,pci-gart.c] to better show the changes necessary to adapt those files to Xen. They were included with the patch and should not be applied again. -Mark Langsdorf AMD, Inc. --- pristine-linux-2.6.12/arch/x86_64/kernel/aperture.c 2005-06-17 12:48:29.000000000 -0700 +++
2013 Nov 19
23
[PATCH v6 00/16] xen: arm: 64-bit guest support and domU FDT autogeneration
Biggest change is to switch the new DTB node to /xen-core-devices instead of /xen at Stefano''s request. I also dropped the few patches title HACK etc which weren''t supposed to be there and fixed up some bits and pieces which folks commented on. George, WRT the freeze I think this is functionality which we cannot ship Xen 4.4 without. The impact is entirely constrained to the
2013 Nov 01
17
[PATCH v2 00/14] xen: arm: 64-bit guest support and domU FDT autogeneration
I''ve addressed all (I think/hope) of the review comments. The main change is to expose the guest virtual platform (e.g. memory layout and interrupt usage etc) to the toolstack via the public interface. This is then used during FDT generation. I have just codified the current defacto standard layout, it''s probably not the best layout but any change can be a separate patch/series.
2013 Dec 01
70
[PATCH 00/13] Coverity fixes for libxl
Matthew Daley (13): libxl: fix unsigned less-than-0 comparison in e820_sanitize libxl: check for xc_domain_setmaxmem failure in libxl__build_pre libxl: correct file open success check in libxl__device_pci_reset libxl: don''t leak p in libxl__wait_for_backend libxl: remove unsigned less-than-0 comparison libxl: actually abort if initializing a ctx''s lock fails libxl:
2012 Oct 20
15
xen-unstable, winxp32 very poor performance on AMD FX-8150, I bisected and changeset is 24770:7f79475d3de7
I ran a bisect to find out when Windows XP 32 bit becomes unusably slow. And I found the changeset that caused it. ========== The problem: ========== Windows 8 64 bit and 32 bit run fast and fine in the newest xen versions. Windows XP 32 bit runs unusably slow in anything new that I built from xen-unstable, but runs fast in 4.1.2 and 4.1.3 stable. While it is running slow, "xm top" or
2013 Jan 23
132
[PATCH 00/45] initial arm v8 (64-bit) support
First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I
2010 Aug 05
0
[GIT PULL] x86/mm for 2.6.36
Hi Linus, The following changes since commit 540ad6b62b3a188a53b51cac81d8a60d40e29fbd: Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/linux-2.6-kgdb (2010-07-28 20:01:26 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git x86-mm-for-linus Andres Salomon (1): x86, mm: Create
2020 Jul 18
25
[PATCH 00/12] Bunch of patches for cross-compilatio + RP4
Initially out there as #965245. I strongly prefer to build ARM64 packages on non-ARM systems. Something about my main build machine having twice the cores and twice the clock speed. As such after many builds I've managed to generate a set of patches which appear to mostly function to get functioning cross-builds of Xen. These are NOT a 100% solution. Some packaging hacks were needed. In
2013 Feb 22
48
[PATCH v3 00/46] initial arm v8 (64-bit) support
This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.
2011 Nov 08
48
Need help with fixing the Xen waitqueue feature
The patch ''mem_event: use wait queue when ring is full'' I just sent out makes use of the waitqueue feature. There are two issues I get with the change applied: I think I got the logic right, and in my testing vcpu->pause_count drops to zero in p2m_mem_paging_resume(). But for some reason the vcpu does not make progress after the first wakeup. In my debugging there is one