Displaying 20 results from an estimated 100 matches similar to: "combining two different matrizes"
2004 Oct 29
1
[rmetasim] Need help deciphering this error msg... targeted to those who use rmetasim...
Hello,
I am trying to do some simulation using the rmetasim
package and I've run to this problem.
--beginning of error msg--
Error in "[<-"(`*tmp*`, slice[l, ], slice[l, ], value
= c(0.200000002980232, :
number of items to replace is not a multiple
of replacement length
--end of error msg--
Here is the script I used.
--script starts here--
## load 'rmetasim'
2010 Aug 05
1
Error in as.environment(pos): using 'as.environment(NULL)' is defunct
Hello,
I?m using R 2.11.1 with Tinn-R 1.17.2.4.
I hope the given informations are enough (it?s my first entry here)
The as.environment(pos) error appears in using the following code which
should open a function in an other R-file.
Here some extractions of the code:
....
HZ<-tclVar(seq(length=a,from=1,by=0)) #(a is defined by a
tkentry-element)
VZ<-tclVar(seq(length=a,from=1,by=0))
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
On Mar 19, 2010, at 10:28 AM, Chris Lattner wrote:
>
> On Mar 19, 2010, at 7:46 AM, Jakob Stoklund Olesen wrote:
>
>> Hi,
>>
>> After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
>>
>> // A list of registers separated by comma. Used by load/store multiple.
>> def
2010 Mar 22
0
[LLVMdev] Instruction with variable number of outputs
On Mar 19, 2010, at 11:04 AM, Jakob Stoklund Olesen wrote:
>>> The description should only have 4 operands + variable_ops.
>>>
>>> How can you specify a named, variable list of output operands?
>>
>> Why do you need to do this? You currently can't do it.
>
> Because an instruction like LDM loads a variable number of registers. When it specifies
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
Hi,
After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
let PrintMethod = "printRegisterList";
}
def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
reglist:$dsts,
2009 Jan 22
1
looping over a string
Hi list,
I'm using R 2.8.1 under Windows vista. I have the following problem:
First of all I create a string-vector. Then I "convert" these strings
into variables and assign a vector of numeric values. So far
everything's fine.
Now I want to do nearly the same again: I create another string-vector
and I want to assign the variance. So I have to loop over the first
2010 Mar 19
0
[LLVMdev] Instruction with variable number of outputs
On Mar 19, 2010, at 7:46 AM, Jakob Stoklund Olesen wrote:
> Hi,
>
> After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like:
>
> // A list of registers separated by comma. Used by load/store multiple.
> def reglist : Operand<i32> {
> let PrintMethod = "printRegisterList";
> }
2011 Jul 29
3
Problems with ks.test()
Hi,
I got two data point vectors. Now I want to make a ks.test(). I you print
both vectors you will see, that they fit pretty fine. Here is a picture:
http://www.jochen-bauer.net/downloads/kstest-r-help-list-plot.png
As you can see there is one histogram and moreover there is the gumbel
density
function plotted. Now I took to bin-mids and the bin-height for vector1 and
computed the
2014 Jan 19
2
[LLVMdev] Why make the register list a dag for RegisterClass in target descriptor file?
The blow snippet in target.td shows the regList in RegisterClass is typed
as dag. Why not make it a simple list, such as list<Register>?
class RegisterClass<string namespace,
list<ValueType> regTypes, int alignment, dag regList>
Thanks,
-Thomson
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2018 Dec 04
2
MC Assembler / tablegen: actually parsing variable_ops
variable_ops is used in the tablegen defs for many targets to denote
instructions that a variable number of inputs, but it seems that there
aren't any targets for which this results in variable elements in the
instruction encoding (and thus in assembler parsing), since the tablegen
generated assembly matcher ($(Target)GenAsmMatcher.inc) simply assumes that
variable_ops are not to be parsed
2002 Jul 03
3
latex
Hi,
i'm a newbie with latex and postscript but recognize
the power in combination wit R .
...current i don't now how i have to "inform" R1.5.0(patched) about my
MikeTex installation on windows 2000 and get following
latex(table)
Warning messages:
1: cat not found
2: cd not found
3: xdvi not found
P.S. maybe i must define in Rprofile something ???
Thanks for help and
2010 Nov 23
1
Possibility for memory improvement: x <- as.vector(x) always(?) duplicates
Hi,
I've noticed that as.vector() always allocates a new object, e.g.
> x <- 1:10;
> x <- as.vector(x);
> tracemem(x);
[1] "<0x0000000005622db8"
> x <- as.vector(x);
tracemem[0x0000000005622db8 -> 0x0000000005622ec0]: as.vector
> x <- as.vector(x);
tracemem[0x0000000005622ec0 -> 0x0000000005622f18]: as.vector
> x <- as.vector(x);
2015 Aug 31
2
MCRegisterClass mandatory vs preferred alignment?
On 08/31/2015 03:59 PM, Matthias Braun wrote:
> Looks to me like the alignment is specified in tablegen. From Target.td:
>
> class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
> dag regList, RegAltNameIndex idx = NoRegAltName>
>
> X86RegisterInfo.td:
>
> def VR256 : RegisterClass<"X86", [v32i8,
2012 Sep 26
2
[LLVMdev] Distinguish variadic register defines/uses in MCInstrDesc?
Am Mittwoch, 26. September 2012, 11:18:20 schrieb Jakob Stoklund Olesen:
> Hi Christoph,
>
> As you noticed, MCInstrDesc doesn't distinguish between variadic uses and
> defs. Since variadic instructions will always require some kind of special
> handling, it doesn't seem worthwhile to make the model more detailed.
I don't see what makes them so different from other
2015 Aug 31
3
MCRegisterClass mandatory vs preferred alignment?
Looking around today, it appears that TargetRegisterClass and
MCRegisterClass only includes a single alignment. This is documented as
being the minimum legal alignment, but it appears to often be greater
than this in practice. For instance, on x86 the alignment of %ymm0 is
listed as 32, not 1. Does anyone know why this is?
Additionally, where are these alignments actually defined? I
2011 Nov 30
2
[LLVMdev] Register allocation in two passes
Thanks for all the hints Jakob, I've added the following piece of code
after the spill code handling inside selectOrSplit() (ignoring some control
logic):
for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I !=
E;
++I)
{
unsigned VirtReg = I->first;
if ((TargetRegisterInfo::isVirtualRegister(VirtReg))
&& (VRM->getPhys(VirtReg)
2009 Nov 13
2
linear model and by()
Hello R list,
This is a question for anyone who has used the by() command. I would like to
perform a regression on a data frame by several factors. Using by() I think
that I have able to perform this using the following:
> lm.r <- by(master, list(Sectionf=Sectionf, startd=startd), function(x) lm
(tot.c ~ starttime, data = x))
So that is, I would like to perform separate regressions for
2006 Jan 16
1
How to analysis Y98 chips using RankProd package?
Dear R and Bioconductor Helpers,
I am using a package called RankProd under Bioconductor to analysis my
Y98 (yeast) microarray data. I had no problem following the example in
the vignette but got stocked when I tried to analyze my own data.
When I tried to run the following command,
RP.out <- RP(rrf.sub, rrf.cl.sub, gene.names = y98.gnames, rand = 123)
I got the following response:
Rank
2012 Oct 05
0
[LLVMdev] Distinguish variadic register defines/uses in MCInstrDesc?
Hallo,
I worked on how to handle the distinction between variadic defines and uses
and my current solution is this:
I introduce a new dag item in Instruction called VariadicOperandList, which by
default is undefined. It keeps a marker variable_* and all operands which are
placeholders for variable lists (like 'reglist' on ARM).
I think it's the cleanest solution to keep them in a
2003 Apr 17
3
win ME/Samba connection
Ok, believe it or not, I've looked through all 209 pages of the
Samba-HOWTO_Collection.pdf plus used this mail list and other internet
sources, used those recommendations, tried almost every possible
iteration on the samba.conf file, looked at logs until nauseated and
have concluded that there is no way that Windows ME can connect to a
Linux box using Samba. Connecting to the WinME box from