similar to: Scheduler Mechnisms!

Hello, This is a question about diffserv on linux. We know, there is a file sch_dsmark in linux source code. Now, i want to add something in the function dsmark_enqueue, for example, i want to add a function which can add a class and queue automately in dsmark_enqueue. That is, not using the command tc. After adding one, it works well, but when add the second one, there is a kernel panic:

Hi, A thought for the list. As I mentioned in another posting, there are a lot of QoS mechanisms out there. Linux supports some, but not all. Some patchsets add others, but don''t work for all kernels. There are also userland implementations, usually sitting in software routers, but there are other packages. Would it be helpful if I worked on a table of what''s out there for

On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote: > Hello LLVM people, > > Our customizable TTA target [1] is capable of having plenty of > registers > and register file ports to improve instruction level parallelism and > reduce spills. It's totally up to the designer of the particular TTA > processor how much the processor has registers and register file >

Is there a document describing the guts of SCEV anywhere? I have a simple question. When looking at a linear SCEVAddRecExpr with a constant step recurrence (that is, getStepRecurrence returns SCEVConstant), is the constant in terms of bytes or in terms of "index," in that the byte offset is calculated by taking the step and multiplying it by the data size of any memory operation its

Gordon Henriksen wrote: > Can you be more specific the algorithm for which you need type > metadata in a write barrier? No algorithms I am aware of perform any > tracing from a write barrier. > This one does: http://citeseer.ist.psu.edu/cache/papers/cs2/442/http:zSzzSzwww.cs.technion.ac.ilzSz~erezzSzPaperszSzms-sliding-views.pdf/an-on-the-fly.pdf > Write barriers are

On Tue, 26 Jun 2007, [ISO-8859-1] Alberto González wrote: > The problem is that what i'm instrumenting is loads and stores, plus > function call arguments and return values, which have no signedness > information. Why do you need this? -Chris > El 26/06/2007, a las 17:03, Anton Korobeynikov escribió: > >> Hello, Alberto. >> >>> I'm using llvm for

>> As part of the advanced compilers course semester project (at >> UIUC), we >> are starting to implement array dependence analysis for LLVM. Great! This is something we've needed for a long time. > I'm currently working on a similar project and hoping to finish it in > about two weeks. Cool! I think the most critical part of this is to get a good

Hello LLVM people, Our customizable TTA target [1] is capable of having plenty of registers and register file ports to improve instruction level parallelism and reduce spills. It's totally up to the designer of the particular TTA processor how much the processor has registers and register file resources along with other TTA components. We have ported LLVM 2.1 to produce an intermediate TTA

I appreciate your suggestions, some follow-up questions though.... >1) LLVM has the capabilities to do everything that you are trying to >re-implement. >2) Have you looked at the C backend? It recreates loops. It may not >create "for" loops but you can hack on it to do that. I wonder if you mean "goto elimination technique" by Ana Maria Erosa (

Chris Lattner wrote: > On Thu, 12 Apr 2007, Fernando Magno Quintao Pereira wrote: >>> I'm definitely interested in improving coalescing and it sounds like >>> this would fall under that work. Do you have references to papers >>> that talk about the various algorithms? >> Some suggestions: >> >> @InProceedings{Budimlic02, >> AUTHOR =

Toward a better register allocator, I'm attempting to understand the dataflow information available to the allocator. What's the difference between LiveInterval information and LiveVariable information? If a LiveInterval is based on a linear ordering of the machine instructions, isn't it rather conservative in nature? Let's say I have a typical diamond CFG: A

Hi, > Is there a document describing the guts of SCEV anywhere? If you're looking for theoretical background of SCEV (chains of recurrences algebra), you may take a look at this article: http://citeseer.ist.psu.edu/vanengelen00symbolic.html I'm not aware of any LLVM-specific document describing SCEV. > I have a simple question. When looking at a linear SCEVAddRecExpr > with a

On 25 Feb 2015, at 20:59, Peter Mogensen <apm at one.com> wrote: > So, why not just extend the support for proxy authentication forwarding > to any single-handskake SASL-IR mechanism, which doesn't use > channel-binding? (which includes PLAIN, but also GS2-KRB5, and possibly > others). Yeah, I guess it would work for several of the auth mechanisms. It's a lot of work

Hello there, apologies for cross-posting my question is not an S/R question but there is so much knowledge concentrated in those lists that I thought someone could point me in the right direction. A few months ago I read an article in a referenced journal comparing some data mining programs, among which there was Insightful's I Miner, SAS' Entreprise Miner, SPSS' Clementine (I think)

Are there any examples of bvt scheduler parameters usage? If I understand it right, bvt provides me with option to scale domain''s CPU usage. Eg. I have 2 (non-zero) domains pinned to the same CPU. Can I assign eg. 30% of CPU time to domain 1 and 70% to domain 2? (I mean in peaks when both domains are not idle and require the CPU time) If yes, how should I build the "xm bvt"

Hi, > Cool! I think the most critical part of this is to get a good > interface for dependence analysis. There are lots of interesting > implementations that have various time/space tradeoffs. > > For example, it would be great if Omega was available as an option, > even if the compiler didn't use it by default. This argues for making > dependence analysis

I'm using LLVM to instrument C code to test the efectiveness of some methods of error detection with dynamic invariants (see http:// citeseer.ist.psu.edu/hangal02tracking.html). I'm using also a range invariant (max an min values seen). The problem is that for those invariants, I need to know if the value is signed or not (0xFF can be -1 or 255, depending on signed/unsigned).

Hi, I understand from earlier discussions that the reason dovecot doesn't support proxying of other SASL mechanisms than those which supply the plaintext password is that in general it would be possible to proxy any SASL mechanism since it might protect against man-in-the-middle attacks (which would prevent proxying). However, that has led to choice between letting users use PLAIN (or

Ralf, Ok, thanks, I'll have a look. The paper I was referencing was http://citeseer.ist.psu.edu/viewdoc/summary?doi=10.1.1.94.668 from '90 I believe. There is also an Intel paper the expands on this for the Itanium. On Fri, Jan 6, 2012 at 12:34 PM, Ralf Karrenberg < karrenberg at cdl.uni-saarland.de> wrote: > Hi, > > I am not sure if I know the paper you mentioned, but

On 2007-09-15, at 23:55, Talin wrote: > Gordon Henriksen wrote: > >> Can you be more specific the algorithm for which you need type >> metadata in a write barrier? No algorithms I am aware of perform >> any tracing from a write barrier. > > This one does: > > http://citeseer.ist.psu.edu/cache/papers/cs2/442/ >