similar to: [PATCH] mkfs.btrfs on ARM

Commit-ID: 59f3f33338f371b3a30163406fbb5fe323503939 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=59f3f33338f371b3a30163406fbb5fe323503939 Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 08:33:02 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips/mips64: simplify

Commit-ID: 3438d861da2e6939a6b0d454ffe247c19ead5993 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=3438d861da2e6939a6b0d454ffe247c19ead5993 Author: Dejan Latinovic <Dejan.Latinovic at imgtec.com> AuthorDate: Thu, 5 Mar 2015 16:51:45 -0800 Committer: H. Peter Anvin <hpa at linux.intel.com> CommitDate: Thu, 5 Mar 2015 16:51:45 -0800

[mod: The first message would''ve been rejected on the grounds "no security related information", but it gives ME a warm feeling too, so I''m allowing it to piggyback on the announcement of the "fix". Note that Linux-2.1.63 simply implements a fix for the problem, instead of applying this fix, upgrading to 2.1.63 might be an option for you. Linus indicated that

ya trivial series... Joe Perches (44): arch/arm: Remove unnecessary semicolons arch/microblaze: Remove unnecessary semicolons arch/um: Remove unnecessary semicolons drivers/cpufreq: Remove unnecessary semicolons drivers/gpio: Remove unnecessary semicolons drivers/i2c: Remove unnecessary semicolons drivers/isdn: Remove unnecessary semicolons drivers/leds: Remove unnecessary

ya trivial series... Joe Perches (44): arch/arm: Remove unnecessary semicolons arch/microblaze: Remove unnecessary semicolons arch/um: Remove unnecessary semicolons drivers/cpufreq: Remove unnecessary semicolons drivers/gpio: Remove unnecessary semicolons drivers/i2c: Remove unnecessary semicolons drivers/isdn: Remove unnecessary semicolons drivers/leds: Remove unnecessary

ya trivial series... Joe Perches (44): arch/arm: Remove unnecessary semicolons arch/microblaze: Remove unnecessary semicolons arch/um: Remove unnecessary semicolons drivers/cpufreq: Remove unnecessary semicolons drivers/gpio: Remove unnecessary semicolons drivers/i2c: Remove unnecessary semicolons drivers/isdn: Remove unnecessary semicolons drivers/leds: Remove unnecessary

ya trivial series... Joe Perches (44): arch/arm: Remove unnecessary semicolons arch/microblaze: Remove unnecessary semicolons arch/um: Remove unnecessary semicolons drivers/cpufreq: Remove unnecessary semicolons drivers/gpio: Remove unnecessary semicolons drivers/i2c: Remove unnecessary semicolons drivers/isdn: Remove unnecessary semicolons drivers/leds: Remove unnecessary

On Wed, Sep 16, 2015 at 01:50:08PM +0530, Sudip Mukherjee wrote: > Hi, > While crosscompiling the kernel for openrisc with allmodconfig the build > failed with the error: > drivers/vhost/vhost.c: In function 'vhost_vring_ioctl': > drivers/vhost/vhost.c:818:3: error: call to '__compiletime_assert_818' declared with attribute error: BUILD_BUG_ON failed: __alignof__

dmesg [ 9007.285922] nouveau 0000:01:00.0: volt: couldn't set 887500uv [ 9007.285930] nouveau 0000:01:00.0: clk: failed to raise voltage: -22 [ 9007.285933] nouveau 0000:01:00.0: clk: error setting pstate 1: -22 [ 9333.740189] nouveau 0000:01:00.0: volt: couldn't set 825000uv [ 9333.740196] nouveau 0000:01:00.0: clk: failed to raise voltage: -22 [ 9333.740200] nouveau 0000:01:00.0: clk:

Instruction selection happens on a different IR: SelectionDAG. In this IR, there are sign-extending loads that the IR converter will use, and are used for example to load 8/16-bit values into 32-bit registers (with sign or zero extension). Any optimizations performed during codegen will be in this representation, or even MachineInstr form, which is post-isel and any sign-extension information

This small patchset adds const to of_device_id arrays in drivers branch. Fabian Frederick (35): ata: constify of_device_id array regulator: constify of_device_id array thermal: constify of_device_id array tty/hvc_opal: constify of_device_id array tty: constify of_device_id array power: constify of_device_id array char: constify of_device_id array dma: constify of_device_id array

This small patchset adds const to of_device_id arrays in drivers branch. Fabian Frederick (35): ata: constify of_device_id array regulator: constify of_device_id array thermal: constify of_device_id array tty/hvc_opal: constify of_device_id array tty: constify of_device_id array power: constify of_device_id array char: constify of_device_id array dma: constify of_device_id array

Hi all, when compiling code like short ptr * = some_address; int val; val = *ptr; if (val>2047) val = 2047; else if (val<-2048) val = -2048. // other things done that require val to be an int ... The load operation is represented by a load and a sign extension operation in the LLVM IR. On most target architectures, there exist signed halfword load instructions, so the load and

On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter < bjorn.desutter at elis.ugent.be> wrote: > On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> > wrote: > > Instruction selection happens on a different IR: SelectionDAG. In this > IR, there are sign-extending loads that the IR converter will use, and are > used for example to load 8/16-bit

From: Wade Cline <clinew@linux.vnet.ibm.com> This patch is only an RFC. My internship is ending and I was hoping to get some feedback and incorporate any suggestions people may have before my internship ends along with life as we know it (this Friday). The filesystem should mount/umount properly but tends towards the explosive side when writes start happening. My current focus is on

On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote: > Instruction selection happens on a different IR: SelectionDAG. In this IR, there are sign-extending loads that the IR converter will use, and are used for example to load 8/16-bit values into 32-bit registers (with sign or zero extension). Any optimizations performed during codegen will be in this

Turned out to be a rather simple fix. Just copied SP to a virtual register in the beginning of the function. Then added an extra operand to the DAGs with stack reference load/store, with the extra operand equal to this virtual register if the Parent of the address is a LOAD/STORE of an 8 or 16 bit quantity. It worked fine. When needed SP got copied to a mips 16 register and when the SP alias

Trying to think of a clever way to do something.... On Mips 16, the SP (stack pointer) is not a directly accessible register in most instructions. There is a way to move to and from mips 16 registers (subset of mips32) and mips32 registers. For the load/store word instructions, there are forms which implicitly take SP. However, for store/load byte and store/load halfword, there is no such

On Jan 21, 2013, at 6:34 AM, Justin Holewinski <justin.holewinski at gmail.com> wrote: > > On Mon, Jan 21, 2013 at 9:16 AM, Bjorn De Sutter <bjorn.desutter at elis.ugent.be> wrote: > On 21 Jan 2013, at 14:39, Justin Holewinski <justin.holewinski at gmail.com> wrote: > >> Instruction selection happens on a different IR: SelectionDAG. In this IR, there are

restructure try_release_extent_buffer() and write a function to release the extent buffer. It will be used later. Signed-off-by: Miao Xie <miaox@cn.fujitsu.com> --- fs/btrfs/extent_io.c | 48 +++++++++++++++++++++++++++++++++++++----------- 1 files changed, 37 insertions(+), 11 deletions(-) diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c index 41277d6..70b7cc5 100644 ---