similar to: [PATCH V2] xen/arm: implement smp_call_function

smp_call_function and smp_call_function_single are almost complete duplicates of the same logic. This patch combines them by implementing them in terms of the more general smp_call_function_mask(). [ Jan, Andi: This only changes arch/i386; can x86_64 be changed in the same way? ] [ Rebased onto Jan's x86_64-mm-consolidate-smp_send_stop patch ] Signed-off-by: Jeremy Fitzhardinge

smp_call_function and smp_call_function_single are almost complete duplicates of the same logic. This patch combines them by implementing them in terms of the more general smp_call_function_mask(). [ Jan, Andi: This only changes arch/i386; can x86_64 be changed in the same way? ] [ Rebased onto Jan's x86_64-mm-consolidate-smp_send_stop patch ] Signed-off-by: Jeremy Fitzhardinge

Rename the existing gic_dump_info to gic_dump_info_guest reduce confusion. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- v2: s/gic_dump_info/gic_dump_info_guest/ --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/gic.c | 77 ++++++++++++++++++++++++++++++++++++++++++++- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 78 insertions(+), 3 deletions(-) diff

Short of getting an explanation for the odd difference to native, make the code match native (and also, in the case of x86-64, __smp_call_function_single()). As usual, written and tested against 2.6.24-rc3 and made apply against 2.6.18 without further testing. Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: head-2007-11-30/arch/i386/kernel/smp-xen.c

# HG changeset patch # User Boris Ostrovsky <boris.ostrovsky@amd.com> # Date 1345135101 -7200 # Node ID 85190245a94d9945b7656c971ba36f7d1eff5c19 # Parent 6d56e31fe1e1dc793379d662a36ff1731760eb0c AMD, powernow: Update P-state directly when _PSD''s CoordType is DOMAIN_COORD_TYPE_HW_ALL When _PSD''s CoordType is DOMAIN_COORD_TYPE_HW_ALL (i.e. shared_type is

Currently, enable/disable turbo mode on AMD is broken: $ xenpm enable-turbo-mode 0 <-- works and proper CPU MSR bit is set $ xenpm enable-turbo-mode 1 <-- silently broken, MSR bit not set Since ->turbo is per policy, when user requests to enable/disable turbo mode, we need to set the bit in all of the ->cpus that this policy affects. --- xen/arch/x86/acpi/cpufreq/powernow.c | 2

Attached and below are a patch that unifies the shutdown code paths in Xen, including those from EARLY_FAIL. This will facilitate the use of Intel(R) TXT for measured launch by ensuring that all shutdowns will call the necessary hook to tear down the measured environment. It also centralizes any future shutdown-related changes. The patch also postpones clearing the online status APs in

This adds an smp_ops for voyager, and hooks things up appropriately. This is the first baby-step to making subarch runtime switchable. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: James Bottomley <James.Bottomley@HansenPartnership.com> Cc: Eric W. Biederman <ebiederm@xmission.com> --- arch/i386/kernel/Makefile | 1 arch/i386/kernel/smp.c

This adds an smp_ops for voyager, and hooks things up appropriately. This is the first baby-step to making subarch runtime switchable. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: James Bottomley <James.Bottomley@HansenPartnership.com> Cc: Eric W. Biederman <ebiederm@xmission.com> --- arch/i386/kernel/Makefile | 1 arch/i386/kernel/smp.c

We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0 vcpu0 is running on pcpu1 for example (you can test this

Hi, This is the fifth version of this patch series. With the Versatile Express TC2, it''s possible to boot only with A7 or A15. If the user choose to boot with only A7, the CPU ID will start at 0x100. As Xen relies on it to set the logical ID and the GIC, it won''t be possible to use Xen with this use case. This patch series is divided in 3 parts: - Patch 1: prepare Xen

We need to write the irq number to GICC_DIR on the physical cpu that previously received the interrupt, but currently we are doing it on the pcpu that received the maintenance interrupt. As a consequence if a vcpu is migrated to a different pcpu, the irq is going to be EOI''ed on the wrong pcpu. This covers the case where dom0 vcpu0 is running on pcpu1 for example (you can test this

Currently cpufreq and xenpm are out of sync. Fix cpufreq reporting of if turbo mode is enabled or not. Fix xenpm to not decode for tristate, but a boolean. Signed-off-by: Jacob Shin <jacob.shin@amd.com> --- tools/misc/xenpm.c | 14 +++----------- xen/drivers/cpufreq/utility.c | 2 +- 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/tools/misc/xenpm.c

Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers at canonical.com> --- This is mostly just for testing, although it should be safe to apply to nouveau trunk. src/nouveau_dri2.c | 34 +++++++++++ src/nv_driver.c | 163 +++++++++++++++++++++++++++++++++++++++++++++++----- src/nv_type.h | 7 +++ 3 files changed, 191 insertions(+), 13 deletions(-) diff

Add basic infrastructure for xen power management. Now only S3 (suspend to ram) is supported. Signed-off-by Ke Yu <ke.yu@intel.com> Signed-off-by Kevin Tian <kevin.tian@intel.com> diff -r 13e258a58044 xen/arch/x86/acpi/Makefile --- a/xen/arch/x86/acpi/Makefile Wed Feb 14 11:13:40 2007 +0800 +++ b/xen/arch/x86/acpi/Makefile Wed Feb 14 11:13:40 2007 +0800 @@ -1,1 +1,2 @@ obj-y +=

v2: Fix build against Xservers without Wayland support Don't try to acquire/drop drm master under Wayland Refresh for xserver 1.13 kill-all-direct-access-to-xf86Screens Remove #ifdef soup in favour of xwayland compat header Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers at canonical.com> --- configure.ac | 7 ++ src/Makefile.am |

A NO_IDLE_HZ implementation is provided for i386 VMI builds. When a VCPU enters its idle loop, it disables its periodic alarm and sets up a one shot alarm for the next time event. That way, it does not become ready to run just to service the periodic alarm interrupt. Instead, it can remain halted until there is some real work pending for it. This allows the hypervisor to use the physical

A NO_IDLE_HZ implementation is provided for i386 VMI builds. When a VCPU enters its idle loop, it disables its periodic alarm and sets up a one shot alarm for the next time event. That way, it does not become ready to run just to service the periodic alarm interrupt. Instead, it can remain halted until there is some real work pending for it. This allows the hypervisor to use the physical

# HG changeset patch # User Ian Campbell <ian.campbell@citrix.com> # Date 1254298855 0 # Node ID 5215da46d60f95d57244e709cb3b189caffec50c # Parent 6472342c8ab0789b844714bcf557e9e5eeacca42 Disable HPET broadcast mode on kexec. Without this the new kernel cannot receive timer interrupts from the legacy sources. Hangs are observed in the second kernel''s "check_timer()"

1: x86/mwait_idle: remove assumption of one C-state per MWAIT flag 2: x86/mwait_idle: export both C1 and C1E 3: x86/mwait_idle: initial C8, C9, C10 support Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Jan Beulich <jbeulich@suse.com>