similar to: [PATCH V2] nouveau: Allow 3D accelerators with output ports

This patch let's cards with PCI class 0x30200 (3D controller) be operated by the nouveau driver as well. The nv Quadro NVS 450 is one such card, where the first GPU has PCI class 0x30000 and the other GPU has PCI class 0x30200. By ignoring the 1 << 9 bit in the PCI class mask, displays attached to the other GPU can also be used now. Signed-off-by: Marek Vasut <marex at denx.de>

Here are a few patches adding some missing functions in NvPlatformProbe, which iirc is being used as of xserver 1.13 First patch adds a nouveau_kernel_mode_enabled helper, similar to xf86-video-radeon Second and third use the function in Nv{Pci,Platform}Probe And last one ensures we can still use ZaphodHead and relative head positioning via xorg.conf The coding style may be a bit off, despite my

From: Christopher James Halse Rogers <raof at ubuntu.com> Barring some (admittedly significant) missing optimisations? this is reasonably complete, but can't be applied until the Xserver patch has landed, and that needs more work. This demonstrates the approach, however. There's probably some code to be shared with XWayland support, around the output handling (or lack thereof) and

Anybody using hardware SSL accelerators on CentOS? The architecture that I'm looking at is CentOS 4 32 bit and Tomcat, and the motherboards can accept PCI Express cards. But I'm interested in any observations at all, even on different software and hardware versions - what works for you, what to stay away from, etc. -- Florin Andrei http://florin.myip.org/

I was going to say, this reminds me of Kai's presentation at Fosdem yesterday. https://fosdem.org/2018/schedule/event/heterogenousd/ It's always good to see the cross-architecture power of LLVM being used in creative ways! :) cheers, --renato On 5 February 2018 at 13:35, Nicholas Wilson via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Interesting. > > I do something

Interesting. I do something similar for D targeting CUDA (via NVPTX) and OpenCL (via my forward proved fork of Khronos’ SPIRV-LLVM)[1], except all the code generation is done at compile time. The runtime is aided by compile time reflection so that calling kernels is done by symbol. What kind of performance difference do you see running code that was not developed with GPU in mind (e.g.

HI LLVM comunity, after 3 years of development, various talks on LLVM-HPC and EuroLLVM and other scientific conferences I want to present my PhD research topic to the lists. The main goal for my research was to develop a single-source programming model equal to CUDA or SYCL for accelerators supported by LLVM (e.g., Nvidia GPUs). PACXX uses Clang as front-end for code generation and comes with

On Thu, May 9, 2024 at 3:44?PM Mohamed Ahmed < mohamedahmedegypt2001 at gmail.com> wrote: > Allows PTE kind and tile mode on BO create with VM_BIND, > and adds a GETPARAM to indicate this change. This is needed to support > modifiers in NVK and ensure correctness when dealing with the nouveau > GL driver. > > The userspace modifiers implementation this is for can be found

On Wed, May 8, 2024 at 6:06?PM Mohamed Ahmed < mohamedahmedegypt2001 at gmail.com> wrote: > Allows PTE kind and tile mode on BO create with VM_BIND, > and adds a GETPARAM to indicate this change. This is needed to support > modifiers in NVK and ensure correctness when dealing with the nouveau > GL driver. > > The userspace modifiers implementation this is for can be found

But does it work? --- shared-core/nouveau_reg.h | 248 ++++++++++++++++++++++---------------------- 1 files changed, 124 insertions(+), 124 deletions(-) diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index ea4a2f6..e2b3012 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -25,14 +25,14 @@ # define NV_RAMHT_CONTEXT_VALID

I've targeted Speex to run under eCos with Thumb interworking using arm-elf-gcc 3.3.3 I'd written a small test case to verifiy the operation: #include <speex/speex.h> void speex_test(void) { SpeexBits bits; unsigned int frame_size; void *enc_state; float *speex_frame; cyg_uint64 t1, t2; int i; speex_frame = (float *)0x00030000; /* Address of Speex data

User-space use mappable BOs notably for fences, and expects that a value update by the GPU will be immediatly visible through the user-space mapping. ARM has a property that may prevent this from happening though: memory can be mapped multiple times only if the different mappings share the same caching properties. However all the lowmem memory is already identity-mapped into the kernel with cache

Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h | 882 +++++++++++++-------------- drm/nouveau/nvkm/subdev/pmu/fuc/macros.fuc | 2 +- 2 files changed, 442 insertions(+), 442 deletions(-) diff --git a/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h b/drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h index 8a2b628..11179c1 100644 ---

Hello, has anybody make this game run? I have Fedora Core 2, I installed the wine-0.20040505-1.rhfc2.nr.rpm package from http://newrpms.sunsite.dk/apt/redhat/en/i386/fc2/RPMS.newrpms/ I installed gunbound, updated it to the latest version and when I wine it i see its window all black with the two boxes for the login and password, i enter this information and click in the botton right corner

Fixes failure to compile with recent envyas as a result of the 'movw' alias being removed for v5. A bit of history: v3 only has a 16-bit sign-extended immediate mov op. In order to set the high bits, there's a separate 'sethi' op. envyas validates that the value passed to mov(imm) is between -0x8000 and 0x7fff. In order to simplify macros that load both the low and high word,

From: Karol Herbst <git at karolherbst.de> --- drm/nouveau/nvkm/subdev/pmu/fuc/gf100.fuc3.h | 788 +++++++++++++++------------ drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h | 740 ++++++++++++++----------- drm/nouveau/nvkm/subdev/pmu/fuc/gk104.fuc4.h | 740 ++++++++++++++----------- drm/nouveau/nvkm/subdev/pmu/fuc/gk208.fuc5.h | 710 ++++++++++++++----------

The headers hadn't been regenerated in a long time and had seen a number of manual modifications. A few changes: - remove nvc0_2d entirely, use the nv50 header which has the nvc0 values too - remove 3ddefs, it's identical to the nv50 file - move macros out into a separate file Also the upstream rnndb changed the overall chip naming convention; this was fixed up manually in the

Hi, I've been working a bit on the match interface of CCSM lately and I found that it would be really useful to have features for each match prefix the plugin (core/regex) supports. The feature name is built similar to the image feature names: "matchhandler:" + prefix. For example "matchhandler:title" supports the match prefix "title=". So I made a small patch