similar to: [PATCH 0/4] Add posted interrupt supporting

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

The "APIC-register virtualization" and "virtual-interrupt deliver" VM-execution control has no effect on the behavior of RDMSR/WRMSR if the "virtualize x2APIC mode" VM-execution control is 0. When guest uses x2APIC mode, we should enable "virtualize x2APIC mode" for APICV first. Signed-off-by: Jiongxi Li <jiongxi.li@intel.com> diff --git

Change from v2: re-written code in ''vmx_intr_assist'' into if()/else if() sequence to make code change easy to review. Virtual interrupt delivery avoids Xen to inject vAPIC interrupts manually, which is fully taken care of by the hardware. This needs some special awareness into existing interrupr injection path: For pending interrupt from vLAPIC, instead of direct injection, we

The previous order of relinquish resource is: relinquish_domain_resources() -> vcpu_destroy() -> nvmx_vcpu_destroy(). However some L1 resources like nv_vvmcx and io_bitmaps are free in nvmx_vcpu_destroy(), therefore the relinquish_domain_resources() will not reduce the refcnt of the domain to 0, therefore the latter vcpu release functions will not be called. To fix this issue, we need to

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 _______________________________________________ Xen-devel mailing list

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

SVI should be restored in case guest is processing virtual interrupt while saveing a domain state. Otherwise SVI would be missed when virtual interrupt delivery is enabled. Signed-off-by: Jiongxi Li <jiongxi.li@intel.com> diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index ee2294c..38ff216 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@

In hvm enviroment, acpi failed. why? centos5.1 =================================================== [root@hvm001 ~]# xm dmesg __ __ _____ _ ____ ___ ____ _ ____ \ \/ /___ _ __ |___ / / | |___ \ / _ \___ \ ___| | ___| \ // _ \ \047_ \ |_ \ | | __) |_| (_) |__) | / _ \ |___ \ / \ __/ | | | ___) || |_ / __/|__\__, / __/ | __/ |___) | /_/\_\___|_| |_| |____(_)_(_)_____| /_/_____(_)___|_|____/

Also, correct a copy&paste error in the documentation. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- This patch has been in the XenServer patch queue for a long time. It is more for debugging purposes than anything else, but is still proving to be valuable for tracking down bugs with HVM paging operations. diff -r 5af4f2ab06f3 -r e6ec5b2b717f

Hi, After c/s 18694 changed vHPET to vpt, for single HVM RHEL 5u1 guest idle case, our box will consume ~0.8W more power than before. The reason is two periodical vpts'' expires are hard to be aligned in the 50us soft timer SLOP. So we are considering a vpt specific enhancement which could try to just align periodical timers within vpt. A generic enhancement is to add a new interface

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

This patch adds CR8 virtualization. It''s the initial patch for booting HVM x64 Windows guest, and just let every CR8 access issues vmexit. And later we will do acceleration to it. Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Otherwise we may leak memory when setting up nHVM fails half way. This implies that the individual destroy functions will have to remain capable (in the VMX case they first need to be made so, following 26486:7648ef657fe7 and 26489:83a3fa9c8434) of being called for a vCPU that the corresponding init function was never run on. Once at it, also remove a redundant check from the corresponding

[PATCH 4/8] HVM save restore: vcpu context support Signed-off-by: Zhai Edwin <edwin.zhai@intel.com> save/restore HVM vcpu context such as vmcs diff -r ee20d1905bde xen/arch/x86/domain.c --- a/xen/arch/x86/domain.c Thu Jan 11 16:40:55 2007 +0800 +++ b/xen/arch/x86/domain.c Thu Jan 11 16:46:59 2007 +0800 @@ -573,6 +573,7 @@ int arch_set_info_guest( else {

Implement tsc adjust feature IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logical processor also adds (or subtracts) value X

Hi, Keir, Currently, HVM guests do not have access to performance counters. So it is not possible to use performance analyzer software such as vtune in HVM guest to analyze programme performance. Other usage of performance counters , for example, the NMI watchdog, won''t function either. This patch will enable performance counters in HVM guest. Currently, only Core 2 Duo is implemented.

Why is there an argument returned in the function below (of hvm.h), knowing that there is void? static inline void hvm_init_ap_context(struct vcpu_guest_context *ctxt, int vcpuid, int trampoline_vector) { return hvm_funcs.init_ap_context(ctxt, vcpuid, trampoline_vector); } _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Hi Keir The latest (hybrid) patchset again... Change from v5: Address the comments from Tim. Change from v4: 1. Add support for PV clocksource on HVM. (Replace evtchn enabling with pv clock enabling). 2. Update the patch following Tim''s comments. Change from v3: 1. Minor polish the patchset. Replace several specific is_hvm_pv_evtchn_domain() judgement. 2. Name changed...

Hi, I have been trying to get Hyperthreading to work in a Windows HVM on Xen 4.1.2 as described in ''xmexample.hvm''. I think I have set it up correctly, but I can''t seem to get it to work. There is not much documentation on it and most topics are from years ago. I''m curious to know to whether this functionality is still supposed to work. I''m aware that