similar to: [PATCH V3] libxc, libxenstore: make the headers C++-friendlier

Made the xenctrl.h and xenstore.h easier to use with C++: added ''extern "C"'' statements, moved the definition of enum xc_error_code above it''s typedef, and renamed a ''new'' parameter (''new'' is a C++ keyword). Signed-off-by: Razvan Cojocaru <rzvncj@gmail.com> diff -r 5af4f2ab06f3 -r c273ee1fc8ba tools/libxc/xenctrl.h

XC_INVALID_PARAM such as asking for features unsupported by either xen or guest kernel. XC_OUT_OF_MEMORY no comment ;) Signed-off-by: Gerd Hoffmann <kraxel@suse.de> --- tools/libxc/xenctrl.h | 2 ++ 1 file changed, 2 insertions(+) Index: build-32-unstable-12802/tools/libxc/xenctrl.h =================================================================== ---

http://dovecot.org/releases/2.1/alpha/dovecot-2.1.alpha1.tar.gz http://dovecot.org/releases/2.1/alpha/dovecot-2.1.alpha1.tar.gz.sig So it's time for the first alpha version of Dovecot v2.1. There are no huge intrusive changes, so I expect v2.1.0 to be released this year (maybe even in a few months?) The biggest changes are related to full text search handling. I'll probably still make

http://dovecot.org/releases/2.1/alpha/dovecot-2.1.alpha1.tar.gz http://dovecot.org/releases/2.1/alpha/dovecot-2.1.alpha1.tar.gz.sig So it's time for the first alpha version of Dovecot v2.1. There are no huge intrusive changes, so I expect v2.1.0 to be released this year (maybe even in a few months?) The biggest changes are related to full text search handling. I'll probably still make

Implement tsc adjust feature IA32_TSC_ADJUST MSR is maintained separately for each logical processor. A logical processor maintains and uses the IA32_TSC_ADJUST MSR as follows: 1). On RESET, the value of the IA32_TSC_ADJUST MSR is 0; 2). If an execution of WRMSR to the IA32_TIME_STAMP_COUNTER MSR adds (or subtracts) value X from the TSC, the logical processor also adds (or subtracts) value X

--- src/guestfs-internal.h | 1 + src/libvirt-auth.c | 55 +++++++++++++++++++++++++++++++++++++++++--------- 2 files changed, 46 insertions(+), 10 deletions(-) diff --git a/src/guestfs-internal.h b/src/guestfs-internal.h index 5356920..d81fa6b 100644 --- a/src/guestfs-internal.h +++ b/src/guestfs-internal.h @@ -469,6 +469,7 @@ struct guestfs_h unsigned int nr_supported_credentials;

Following up on #190 [1], I''ve just added a simple patch that allows the manipulation of the TYPES hash from within the Merb module. Use like: Merb.add_mime_type(:png,%w[image/png]) Merb.remove_mime_type(:png) It specifically disallows the removal of the :all MimeType, since content negotiation relies on it. I''m not super wonderful at API design, so comments and

Hi, All Intel QA conducted a full validation for xen 4.1 rc1, it includes VT-x, VT-d, SRIOV, RAS, TXT and xl tools testing. 24 issues were exposed. Refer the bug list, please. We already assigned 14 bugs to Intel developers (which has an ''Intel'' tag in the bug title), most of the rest 10 bugs are related xl command. For the these bugs, need community''s help to fix

about VIRQ &amp; PIRQ what is VIRQ  ?How VIRQ is different from PIRQ ?How VIRQ &amp; PIRQ are related each other ? DISCLAIMER: ----------------------------------------------------------------------------------------------------------------------- The contents of this e-mail and any attachment(s) are confidential and intended for the named recipient(s) only. It shall not attach any

From: Andrey Smetanin <asmetanin at virtuozzo.com> Synic is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI semantics - a message page in the guest memory with 16 256-byte per-SINT message slots - an event

This patchset implements the KVM part of the synthetic interrupt controller (synic) which is a building block of the Hyper-V paravirtualized device bus (vmbus). Synic is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI

This patchset implements the KVM part of the synthetic interrupt controller (synic) which is a building block of the Hyper-V paravirtualized device bus (vmbus). Synic is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI

This patchset implements the KVM part of the synthetic interrupt controller (SynIC) which is a building block of the Hyper-V paravirtualized device bus (vmbus). SynIC is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI

This patchset implements the KVM part of the synthetic interrupt controller (SynIC) which is a building block of the Hyper-V paravirtualized device bus (vmbus). SynIC is a lapic extension, which is controlled via MSRs and maintains for each vCPU - 16 synthetic interrupt "lines" (SINT's); each can be configured to trigger a specific interrupt vector optionally with auto-EOI