similar to: Recursive locking in Xen (in reference to NMI/MCE path audit)

I have just starting auditing the NMI path and found that the oprofile code calls into a fair amount of common code. So far, down the first leg of the call graph, I have found several ASSERT()s, a BUG() and many {rd,wr}msr()s. Given that these are common code, and sensible in their places, removing them for the sake of being on the NMI path seems silly. As an alternative, I suggest that we make

xen/arch/x86/crash.c | 116 ++++++++++++++++++++++++++++++++++----- xen/arch/x86/machine_kexec.c | 19 ++++++ xen/arch/x86/x86_64/entry.S | 34 +++++++++++ xen/include/asm-x86/desc.h | 45 +++++++++++++++ xen/include/asm-x86/processor.h | 4 + 5 files changed, 203 insertions(+), 15 deletions(-) Experimentally, certain crash kernels will triple fault very early

Those two should always be delivered first imo. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/hvm/irq.c +++ b/xen/arch/x86/hvm/irq.c @@ -395,16 +395,16 @@ struct hvm_intack hvm_vcpu_has_pending_i struct hvm_domain *plat = &v->domain->arch.hvm_domain; int vector; - if ( (plat->irq.callback_via_type == HVMIRQ_callback_vector) -

The self_nmi() code cause''s an NMI to be triggered by sending an APIC message to the local processor. However, NMIs are blocked by the VMEXIT, until the next iret or VMENTER. Volume 3 Chapter 27 Section 1 of the Intel SDM states: An NMI causes subsequent NMIs to be blocked, but only after the VM exit completes. As a result, as soon as the VMENTER happens, an immediate VMEXIT happens

Guests other than domain 0 using the console output have previously been controlled by the VERBOSE define, but with no designation of which guest''s output was on the console. This patch converts the HVM output buffering to be used by all domains, line buffering their output and prefixing it with the domain ID. This is especially useful for debugging stub domains. Signed-off-by: Daniel De

Hello! The current MCA/MCE support in Xen is that it dumps the error and panics. In the following concept I propose here, there are two places where Xen has to react on. I) Xen receives a MCE from the CPU and II) Xen receives Dom0 instructions via Hypercall The term "self-healing" below is used in the sense of using the most propriate technique(s) to handle an error such as MPR

On Tue, Jun 23, 2020 at 04:59:14PM +0200, Joerg Roedel wrote: > On Tue, Jun 23, 2020 at 04:53:44PM +0200, Peter Zijlstra wrote: > > +noinstr void idtentry_validate_ist(struct pt_regs *regs) > > +{ > > + if ((regs->sp & ~(EXCEPTION_STKSZ-1)) == > > + (_RET_IP_ & ~(EXCEPTION_STKSZ-1))) > > + die("IST stack recursion", regs, 0); > > +}

On Tue, Jun 23, 2020 at 03:03:22PM +0200, Peter Zijlstra wrote: > On Tue, Jun 23, 2020 at 02:12:37PM +0200, Joerg Roedel wrote: > > On Tue, Jun 23, 2020 at 01:50:14PM +0200, Peter Zijlstra wrote: > > > If SNP is the sole reason #VC needs to be IST, then I'd strongly urge > > > you to only make it IST if/when you try and make SNP happen, not before. > > >

Hello, While working on a fix for the rare-but-possible problem of reentrant NMIs and MCEs, I have discovered that it is sadly possible to generate fake NMIs and MCEs which will run the relevant handlers on the relevant stacks, without invoking any of the other CPU logic for these special interrupts. A fake NMI can be generated by a processor in PIC mode as opposed to Virtual wire mode, with a

Guests other than domain 0 using the console output have previously been controlled by the VERBOSE #define, but with no designation of which guest''s output was on the console. This patch converts the HVM output buffering to be used by all domains except the hardware domain (dom0): stripping non-printable characters, line buffering the output, and prefixing it with the domain ID. This is

Hi I am using oprofile 0.9.3 on xen cs 16540 on an Intel system. When I look at the top "hot" functions, I see p2m_change_type being one of the top function in xen-syms. This function is only in the svm (AMD) code and should not appear on an Intel system. I see that this function is not being clled at all when I am running my apps as I have put printk in the functions and they do

X86: Fix mce offline page bug c/s 19913 break mce offline page logic: For page_state_is(pg, free), it''s impossible to trigger the case; For page_state_is(pg, offlined), it in fact didn''t offline related page; This patch fix the bug, and remove an ambiguous comment. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 808735ebbb59 xen/common/page_alloc.c ---

I have an Intel e1000e NIC which I put into passthrough for an HVM domain under Xen 4.2. All the corresponding hardware protections are enabled on my system (DMA + Interrupt remapping), however, once in a while I get a SERR NMI in dom0 (NMI - PCI sys error (SERR) in xl dmesg). I am wondering about its exact reason. I am thinking in the following way: [+] Under Intel VT-x, interrupts are

Xen/MCE: vMCE injection In our test for win8 guest mce, we find a bug that no matter what SRAO/SRAR error xen inject to win8 guest, it always reboot. The root cause is, current Xen vMCE logic inject vMCE# only to vcpu0, this is not correct for Intel MCE (Under Intel arch, h/w generate MCE# to all CPUs). This patch fix vMCE injection bug, injecting vMCE# to all vcpus. Signed-off-by: Liu,

Jan, This patch just used to stick all 1''s to MCi_CTL, it should not involve much argue, so I sent it separately. Thanks, Jinsong ==================== Xen/MCE: stick all 1''s to MCi_CTL of vMCE This patch is a middle-work patch, prepare for future new vMCE model. It remove mci_ctl array, and keep MCi_CTL all 1''s. Signed-off-by: Liu, Jinsong

On Tue, Jul 14, 2020 at 02:08:47PM +0200, Joerg Roedel wrote: > @@ -489,6 +490,9 @@ DEFINE_IDTENTRY_RAW(exc_nmi) > this_cpu_write(nmi_cr2, read_cr2()); > nmi_restart: > > + /* Needs to happen before DR7 is accessed */ > + sev_es_ist_enter(regs); > + > this_cpu_write(nmi_dr7, local_db_save()); > > nmi_enter(); > @@ -502,6 +506,8 @@

On Tue, Jul 14, 2020 at 02:08:47PM +0200, Joerg Roedel wrote: > @@ -489,6 +490,9 @@ DEFINE_IDTENTRY_RAW(exc_nmi) > this_cpu_write(nmi_cr2, read_cr2()); > nmi_restart: > > + /* Needs to happen before DR7 is accessed */ > + sev_es_ist_enter(regs); > + > this_cpu_write(nmi_dr7, local_db_save()); > > nmi_enter(); > @@ -502,6 +506,8 @@

Boris, Here is the updated patch for determining number of regiter banks on AMD plus a patch removing shared_bank array, as you suggested. Offline/online testing didn''t show any issues. Boris Ostrovsky (2): x86/mce: Replace shared_bank array with is_shared_bank() helper x86/mce: Use MCG_CAP MSR to find out number of banks on AMD arch/x86/kernel/cpu/mcheck/mce_amd.c | 38

Currently, Xen does not support injecting an NMI to HVM guest OS. Adding this feature is necessary for those softwares which depend on NMI to function correctly, such as KDB and oprofile. The attached patch allows NMI to be injected to guest OS in NMIP capable platforms. It also enables to queue an NMI and then inject it as soon as possible. Signed-off-by: Haitao Shan

On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: > > From: Joerg Roedel <jroedel at suse.de> > > Keep NMI state in SEV-ES code so the kernel can re-enable NMIs for the > vCPU when it reaches IRET. This patch is overcomplicated IMO. Just do the magic incantation in C from do_nmi or from here: /* * For ease of testing, unmask