similar to: [PATCH 1/3] x86/hvm: don't use indirect calls without need

Add GS base to the HVM VCPU context returned by xc_vcpu_getcontext() Signed-off-by: Aravindh Puthiyaparambil <aravindh@virtuata.com> diff -r e62ab14d44af -r babbb3e0f4d3 xen/arch/x86/domctl.c --- a/xen/arch/x86/domctl.c Fri Apr 20 11:36:02 2012 -0700 +++ b/xen/arch/x86/domctl.c Fri Apr 20 17:55:49 2012 -0700 @@ -1592,6 +1592,12 @@ void arch_get_info_guest(struct vcpu *v,

Commit 86781624 ("x86_emulate: PUSH <mem> must read source operand just once") corrected the operands of those of the operations of opcode extension group 5 that only read memory from SrcMem to DstMem, but failed to also switch the use of "dst" here to "src". Reported-by: Anthony Perard <anthony.perard@citrix.com> Signed-off-by: Jan Beulich

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

Utilize some of the additions in the prior patches to clean up other code: - keep track of REP prefixes in only one variable - use REX_W in a few more places (instead of a literal number) Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -304,6 +304,10 @@ union vex { ptr[1] = rex |

X86: implement PCID/INVPCID for hvm This patch handle PCID/INVPCID for hvm: For hap hvm, we enable PCID/INVPCID, since no need to intercept INVPCID, and we just set INVPCID non-root behavior as running natively; For shadow hvm, we disable PCID/INVPCID, otherwise we need to emulate INVPCID at vmm by setting INVPCID non-root behavior as vmexit. Signed-off-by: Liu, Jinsong

The aim of this patch is to define a stable way in which PVH is going to do AP bringup. Since we are running inside of a HVM container, PVH should only need to set flags, cr3 and user_regs in order to bring up a vCPU, the rest can be set once the vCPU is started using the bare metal methods. Additionally, the guest can also set cr0 and cr4, and those values will be appended to the default values

This patch adds a facility to block on a particular event channel, for when a domain needs to block, but cannot enable interrupts. A domain uses the call something like this: while (1) { clear_evtchn_pending(evtchn); if (check_for_data(evtchn)) break; HYPERVISOR_block_on(evtchn); } The clear of the pending is needed to ensure that any subsequent calls to block_on() don''t

The first patch really isn''t as much of a follow-up than what triggered the security issues to be noticed in the first place. 1: x86: preserve FPU selectors for 32-bit guest code 2: x86: fix XCR0 handling 3: x86/xsave: adjust state management 4: x86/fxsave: bring in line with recent xsave adjustments The first two I would see as candidates for 4.3 (as well as subsequent backporting,

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

This is a patch repairing a regression in code previously functional in 4.1.x. It appears that, during some refactoring work, calls to hvm_memory_event_cr3 and hvm_memory_event_cr4 were lost. These functions were originally called in mov_to_cr() of vmx.c, but the commit http://xenbits.xen.org/hg/xen-unstable.hg/rev/1276926e3795 abstracted the original code into generic functions up a level in

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

With the x86 instruction emulator no pretty complete, I''d like to re-submit this patch to support cmpxchg16b on x86-64 and at once rename the underlying emulator callback function pointer (making clear that if implemented, it is to operate on two longs rather than two 32-bit values). At the same time it fixes an apparently wrong emulator context initialization in the shadow code.

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):

A character device for accessing (in user-space) pages that have been granted by other domains. Signed-off-by: Derek Murray <Derek.Murray@cl.cam.ac.uk> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel