similar to: [PATCH 2/4] x86/emulator: add emulation of SIMD FP moves

- we used the C4/C5 (first prefix) byte instead of the apparent ModR/M one as the second prefix byte - early decoding normalized vex.reg, thus corrupting it for the main consumer (copy_REX_VEX()), resulting in #UD on the two-operand instructions we emulate Also add respective test cases to the testing utility plus - fix get_fpu() (the fall-through order was inverted) - add cpu_has_avx2,

Utilize some of the additions in the prior patches to clean up other code: - keep track of REP prefixes in only one variable - use REX_W in a few more places (instead of a literal number) Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -304,6 +304,10 @@ union vex { ptr[1] = rex |

Since the emulator now supports a few 256-bit memory operations, this array needs to follow (and the comments should, too). To limit growth, re-order the mmio_large_write_* fields so that the two mmio_large_*_bytes fields end up adjacent to each other. Signed-off-by: Jan Beulich <jbeulich@suse.com> --- a/xen/include/asm-x86/hvm/vcpu.h +++ b/xen/include/asm-x86/hvm/vcpu.h @@ -59,13 +59,13

Commit 86781624 ("x86_emulate: PUSH <mem> must read source operand just once") corrected the operands of those of the operations of opcode extension group 5 that only read memory from SrcMem to DstMem, but failed to also switch the use of "dst" here to "src". Reported-by: Anthony Perard <anthony.perard@citrix.com> Signed-off-by: Jan Beulich

Hey guys, I'm currently investigating broadcasts from the constant pool on Sandy Bridge. I see this comment in llvm/lib/Target/X86/X86ISelLowering.cpp: // Handle the broadcasting a single constant scalar from the constant pool // into a vector. On Sandybridge it is still better to load a constant vector // from the constant pool and not to broadcast it from a scalar. Would anyone

With the x86 instruction emulator no pretty complete, I''d like to re-submit this patch to support cmpxchg16b on x86-64 and at once rename the underlying emulator callback function pointer (making clear that if implemented, it is to operate on two longs rather than two 32-bit values). At the same time it fixes an apparently wrong emulator context initialization in the shadow code.

Hey Michael, Thanks for the legwork! It appears that the stats you listed are for movaps [SSE], not vmovaps [AVX]. I would *assume* that vmovaps(m128) is closer to vmovaps(m256), since they are both AVX instructions. Although, yes, I agree that this is not clear from Agner's report. Please correct me if I am misunderstanding. As I am sure you are aware, we cannot use SSE (movaps)

Copy Ii32 in X86InstrFormats.td rename to Ii64 and change Imm32 to Imm64. Instantiate your instruction inheriting from Ii64. Pass RawFrm to the form parameter. Initial documentation for the encoding system is attached. ~Craig On Wed, Mar 28, 2018 at 4:50 PM, Gus Smith via llvm-dev < llvm-dev at lists.llvm.org> wrote: > I am attempting to create an instruction which takes a single

> It appears that the stats you listed are for movaps [SSE], not vmovaps [AVX]. I would *assume* that vmovaps(m128) is closer to vmovaps(m256), since they are both AVX instructions. Although, yes, I agree that this is not clear from Agner's report. Please correct me if I am misunderstanding. You are misunderstanding [no worries, happens to everyone = )]. The timings I listed were for

On Wed, Jul 31, 2019 at 02:53:06PM +0200, Peter Zijlstra wrote: > On Tue, Jul 30, 2019 at 12:12:54PM -0700, Thomas Garnier wrote: > > if PIE is enabled, switch the paravirt assembly constraints to be > > compatible. The %c/i constrains generate smaller code so is kept by > > default. > > > > Position Independent Executable (PIE) support will allow to extend the

tl;dr, I'd like to add my own instruction, but I'm running into problems due to my lack of x86 encoding/decoding understanding. Hello all. Currently, I'm working on adding my own x86 instruction. I have done this once before; the basic process I used was: 1. Find an unused opcode, e.g. 0xF1 in this table: http://ref.x86asm.net/coder32.html 2. Insert an instruction into

In this patch, we change read_segment_register to take vcpu and regs parameters for PVH (in upcoming patches). No functionality change. also, make emulate_privileged_op() public for later. Signed-off-by: Mukesh Rathor <mukesh.rathor@oracle.com> diff -r 93d95f6dd693 -r 0339f85f6068 xen/arch/x86/domain.c --- a/xen/arch/x86/domain.c Fri Jan 11 16:22:57 2013 -0800 +++ b/xen/arch/x86/domain.c

The maximum instruction length for both x86-32 and x86-64 is 15 bytes (including all prefixes, opcode, ModRM, SIB, displacement, and immediate bytes). This patch adjusts the MAX_INST_LEN to the correct value. This should reduce the size of some variables in the hypervisor code. This patch also does some minor code clean-up in the vm exit handler for VMX. This patch should apply cleanly to hg

Hi, Sorry for the newbie question. I downloaded llvm 1.8a and llvm-gcc3.4, tried out the simple "Hello, World" program but got the following error. My system is RedHat 9 $ ./hello lli: /home//llvm/lib/Target/X86/X86CodeEmitter.cpp:208: unsigned char ModRMByte(unsigned int, unsigned int, unsigned int): Assertion `Mod < 4 && RegOpcode < 8 && RM < 8 &&

Hello, In order to have llvm-3.0 into Debian Wheezy, I have to fix a last build failure under MIPS & MIPSEL. The full mipsel build log is available here: https://buildd.debian.org/status/fetch.php?pkg=llvm-3.0&arch=mipsel&ver=3.0-5&stamp=1324350511 [1] The error is the following: /build/buildd-llvm-3.0_3.0-5-mipsel-jV6EnH/llvm-3.0-3.0/build-llvm/Release/bin/llvm-tblgen -I

On Thu, Nov 8, 2012 at 1:34 AM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > > I actually have confusion in mapping the role of vex_w during > instruction selection. For the moment, lets just consider vex_w and > not memop. > > [1]. What does " def rr : FMA4<>, VEX_W" mean? As per tablegen > description, "rr" now inherits FMA4 and

Hi, Sorry for the newbie question. I downloaded llvm and tried out the simple "Hello, World" program but got the following error. What am I missing? I am running RHAS 3 Update 4 with GCC 3.2.3. Thanks, Bharadwaj $ ./hello lli: /home/proj/skokomish/syadaval/ia32/Sandbox/llvm/lib/Target/X86/X86CodeEmitter.cpp:208: unsigned char ModRMByte(unsigned int, unsigned int, unsigned int):

On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and > "MemOp4" like those of "rm" or "rr" ? > Hey Anitha, The VEX.W bit is used to denote operand order. In other words, this bit allows for a memop to be used as

Just looked up the numbers from Agner Fog for Sandy Bridge for vmovaps/etc for loading/storing from memory. vmovaps - load takes 1 load mu op, 3 latency, with a reciprocal throughput of 0.5. vmovaps - store takes 1 store mu op, 1 load mu op for address calculation, 3 latency, with a reciprocal throughput of 1. He does not list vmovsd, but movsd has the same stats as vmovaps, so I feel it is a

Is there a function that will allow me to run all model iterations if I specify a full model? I am using information criteria to choose between possible candidate models. I have been writing out all possible model combinations by hand, and I am always worried that I am missing models or have made a mistake somewhere. It is also difficult to alter models if I want to change a term. For example,