Displaying 20 results from an estimated 300 matches similar to: "ipfw check-state issue"
2005 Feb 22
1
periodic/security/550.ipfwlimit
550.ipfwlimit check in /etc/periodic/security takes into account only
global/default verbosity limit and does not account for a specific
logging limit set for a particular rule e.g.:
$ ipfw -a l | fgrep log
65000 *521* 41764 deny log logamount *1000* ip from any to any
$ sysctl -n net.inet.ip.fw.verbose_limit
*100*
>From security run output:
ipfw log limit reached:
65000 519
2003 Jun 12
1
NIC has IP, but has "no carrier"
Hello,
My computer is not connecting to the local network with the following
configuration:
dmesg.boot contains the following lines:
-----------------------------------------
vr0: <VIA VT3043 Rhine I 10/100BaseTX> port 0xec00-0xec7f mem
0xfeafbc00-0xfeafbc7f irq 11 at device 12.0 on pci2
vr0: Ethernet address: 00:40:05:a5:00:04
miibus0: <MII bus> on vr0
amphy0: <Am79C873 10/100
2013 May 09
2
[LLVMdev] Predicated Vector Operations
On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote:
> On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote:
>> Jeff Bush <jeffbush001 at gmail.com> writes:
>>
>>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...>
>>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...>
>>> %sum = fadd %tx, %ty
>>> %newvalue
2020 Jun 25
2
How to implement load/store for vector predicate register
Hi, there
I am writing an backend, and I met a problem.
We don't have load/store instructions for vector predicate registers(vpr for short).
The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr.
vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations.
A vr has 512 bits, and
2008 Dec 04
1
rc.firewall: default loopback rules are set up even for custom file
I've just realized that I see in releng/7 something that I did not see
in releng/6 - even if I use a file with custom rules in firewall_type I
still get default loopback rules installed.
I think that this is not correct, I am using custom rules exactly
because I want to control *everything* (e.g. all deny rules come with
log logamount xxx).
--
Andriy Gapon
2020 Jun 26
2
How to implement load/store for vector predicate register
Hi,
I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands.
If I use virtual registers, do I need to mark them as "early clobber"?
I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend.
What is the effect of marking a
2003 Apr 30
6
how to configure a FreeBSD firewall to pass IPSec?
I have a FreeBSD box acting as a firewall and NAT gateway
I would like to set it up to transparently pass IPSec packets -- I have
an IPSec VPN client running on another machine, connecting to a remote network.
Is there a way to do this? I can't find any hints in the man pages.
2007 Dec 24
0
Fwd: Re: IPFW: Blocking me out. How to debug?
>Date: Sun, 23 Dec 2007 06:04:02 -0800 (PST)
>From: Nash Nipples <trashy_bumper@yahoo.com>
>To: freebsd-security@freebsd.org
>Subject: Re: IPFW: Blocking me out. How to debug?
>
>Dear W.D.
>
>oh come on. i have the same problem.
Which problem are we talking about?
cut and paste problem.
>cut and paste logic:
>
>#!/bin/sh
>#1. count packets
>#2.
2011 Dec 02
0
[LLVMdev] RFC: Machine Instruction Bundle
. and yes, one more thing. On some architectures it might be desirable to
know the _order_ of instructions in the packet. That is a bit trickier..
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Evan Cheng
Sent: Friday, December 02, 2011 2:40 PM
To: LLVM Dev
Subject: [LLVMdev]
2007 Dec 20
1
IPFW: Blocking me out. How to debug?
Dear W.D.
Do you understand that by adding the rules into kernel space numbered from zero to sixty five thousand five hundred thirty four
you may alter the behavior of the rule number sixty five thousand five hundred thirty five
can you please define and list the goals you are trying to achieve by altering default rule in the terms you can both explain and understand.
----- Original Message
2011 Dec 03
1
[LLVMdev] RFC: Machine Instruction Bundle
On Dec 2, 2011, at 2:41 PM, Sergei Larin wrote:
> … and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier….
Isn't that just the order of the instructions in the list? I don't see anything that prevents getting the order of instructions. It might require iterator over MIs in the packet. But for
2011 Dec 02
0
[LLVMdev] RFC: Machine Instruction Bundle
Evan,
I will need to comprehend it better, but one small comment right away.
Did we not discuss one more option for bundle implementation - global cycle
ID. We would add an unsigned int field to MI definition representing "global
scheduling cycle". All MIs with the same global cycle value belong to one
group/packet. Zero means unscheduled MI.
That is light weight,
2012 Jan 11
0
[LLVMdev] RFC: Machine Instruction Bundle
Hi Evan,
I just read your proposal and the following discussion for VLIW support and want to share my experience of writing a VLIW back-end for LLVM.
I would not integrate the packetizer into the register allocator super class since it would reduce the flexibility for the back-end developer to add some optimization passes after the packetizer. Instead, I would add the packetizer as a separate
2011 Jul 05
2
[LLVMdev] load/store in IR without stack/heap
Hi all,
Can anyone give an idea to solve my problem? I'm implementing backend part
using LLVM for my research architecture. The main issue is that this
architecture
cannot use stack/heap. So, all the value should be stored in the register.
Given that architecture, load/store instruction in IR uses virtual register
to load/
store the value. For example:
C source code is:
if(...) {
a = 1;
2003 May 13
3
Via EPIA Mini-ITX motherboard
i had such problems on my mini-ITX.
when sharing irq's with video or sound card, network traffic during ogg
playing (for example on nfs) or quick moving windows crashed the
interface. ifconfig down/up resolved the problem.
it has been solved for a while now (i couldn't reproduce this problem) i
think.
regards,
OLivier
Le Jeudi 12 D?cembre 2002 03:45, The Anarcat a ?crit :
>
2003 Apr 25
2
firewalling help/audit
Hi !
First of all, I am sorry if this is not the list for that, but I've been
learning (a little bit...) a way to implement a freeBSD firewall.
So far I came up with a set of rules I would like to show you for commenting.
I am sure there're a lot of errors and/or stupid rules (I am not sure the
rules order is good for what I need) and I would be really pleased if one
could have a look
2007 Dec 13
3
IPFW compiled in kernel: Where is it reading the config?
Hi peeps,
After compiling ipfw into the new 6.2 kernel, and typing "ipfw list",
all I get is:
"65535 deny ip from any to any"
From reading the docs, this might indicate that this is the
default rule. (I am certainly protected this way--but can't
be very productive ;^) )
By the way, when I run "man ipfw" I get nothing. Using this
instead:
2005 Feb 23
0
Fw-up: Re: periodic/security/550.ipfwlimit - diff for RELENG-5]
Almost forgot - diff need ot be appied only on FreeBSD 5 version of 550.ipfwlimit,
but resulting file can be used on both 4 and 5 releases.
On Wed, Feb 23, 2005 at 03:59:51PM +0100, Alexander Leidinger wrote:
Better version then previos, it will not break order of rules.
awk version, it will work on all 4 and 5 releases, at least those, where IPFW enabled ;-)
Also i removed check for
2013 Aug 08
1
[PATCH v2 7/7] Sample Implementation of Intel MIC User Space Daemon.
On Wed, Aug 07, 2013 at 08:04:13PM -0700, Sudeep Dutt wrote:
> From: Caz Yokoyama <Caz.Yokoyama at intel.com>
>
> This patch introduces a sample user space daemon which
> implements the virtio device backends on the host. The daemon
> creates/removes/configures virtio device backends by communicating with
> the Intel MIC Host Driver. The virtio devices currently supported
2013 Aug 08
1
[PATCH v2 7/7] Sample Implementation of Intel MIC User Space Daemon.
On Wed, Aug 07, 2013 at 08:04:13PM -0700, Sudeep Dutt wrote:
> From: Caz Yokoyama <Caz.Yokoyama at intel.com>
>
> This patch introduces a sample user space daemon which
> implements the virtio device backends on the host. The daemon
> creates/removes/configures virtio device backends by communicating with
> the Intel MIC Host Driver. The virtio devices currently supported