similar to: Idct - fpga - improved

Hello people My name is Felipe and I sent a proposal to the Google Summer of Code that the goal is to get a FPGA embeded system decoding Theora Streams in real-time. It was accepted and the mentor is the Ralph Giles. The proposal can be viewd here: http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt There is also a presentation with a better division of the

Hi all, Just a stupid question The IDctSlow function on file idct.c has this line : ip[0] = (ogg_int16_t)((_Gd + _Cd ) >> 0); The ip[0] , _Gd and _Cd are of type ogg_int32_t My question is: The result of (_Gd + _Cd) can be a number with more than 16 bits ? (yes, it can be because they are int32, but the algorithm could guarantee something about that... I dont know...) If

Hi people, As I said before: I did the IDCT to run on the FPGA. My friends from university did the Reconstruction routines running on the FPGA. I'm helping with the LoopFilter, and it is almost there. (all VHDL) I did a small profiling of the libTheora running on a Altera Stratix II device: The processor used was the NIOS II with 8Kb of data and instruction cache, branch prediction and

Hello, First of all, I would like to say that my work that I wrote in the other email would be to do in hardware the functions: CopyRecon, LoopFilter and UpdateUMVBorder. These are modules that Leonardo had made, but it wasn't ok in FPGA. When I had a chat with Leonardo we were thinking in rewrite these module for to do this running in FPGA (to debug in a Hardware level is much more

Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially implemented and the part before will run on a software compiled

Theora hardware with LEON3 is runinng!!! My video was too slow, then I discovered that the problem was on LINUX! I don't exactly, but I suppose that the time of LINUX Call systems (like fread()) is the problem. If I don't use the linux (like is done on NIOS), I can to decode much faster than the time of exibition! Now we have two points on software (the hardware is the same,

Shows that as the MCU increases, the OpenMP extra overhead is amortized and OpenMP becomes as fast as the pthreads implementation. The last chart http://lampiao.lsc.ic.unicamp.br/~piga/gsoc_2008/systime.png Shows that both pthreads and OpenMP overhead decreases as what seems to be a logarithmic function of the MCU size. This was a great experiment, and from what I can conclude, the OpenMP

Hi, I did some improvements and some bug corrections in Theora FPGA code. I'd like to post this new version in the SVN. How can I do that? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956

Hello, I'm happy to announce I developed a Multi-Threaded version of the Theora encoder. I changed the Motion Vector Search part of the algorithm to be executed in parallel. I've chosen the Motion search part after a careful set of profilings that shown that the Motion Vector Search is responsible by 70% of CPU-time on average and up to 95% of CPU-time in some cases. I also have chosen

Hi, I am sending my application I submitted for the GSoC. There are still some hours left before the deadline, so if you have any remarks or a tip, I can still update it. thanks... i think there are some grammatical errors =(... == Name and Contact details == Andr? Luiz Nazareth da Costa Primary e-mail: andre.lnc@gmail.com Secondary e-mail: andre.lnc@lsc.ic.unicamp.br Gtalk:

Hi. I am trying to find calls of idct/fdct.c functions by tracing png2theora.c calls. But found only: analyze.c:oc_dct_cost2() Where and when idct/fdct/mmxidct/mmxfdct.c functions are used? Mentions of "dct" word: ==== pacify at optima-amd64:/usr/src/libtheora-1.2.0alpha1/lib$ grep dct *.c | cut -f1 -d":" | uniq -c ???? 19 analyze.c ???? 28 decode.c ???? 22 encode.c ????? 4

Hi The Theora specification states, in section 7.9.3 ("The 1D Inverse DCT") steps 14-16: 14. Assign T[5] the value T[4] - T[5]. 15. Truncate T[5] to a 16-bit representation by dropping any higher-order bits. 16. Assign T[5] the value C4 * (-T[5]) >> 16. However, the relevant section of code in the reference decoder (lib/dec/idct.c line 50) is:

1) What are you doing "mathematically" in a procedure x86/x86enquant: oc_enc_quantize_sse2()? This - the assembler code, and I do not understand mathematically - that's going on there. --- A: 120 121 28 73 -20 -99 -98 -100 123 122 112 108 73 -32 -102 -98 123 123 117 121 100

So, in preparation for some decoder optimization work planned by Rudolf Marek, the subject of the size of the registers needed in the IDCT came up. The current spec language ensures that the result is exactly compatible with the C code for VP3. This language requires that some of the arguments to the multiplies be 17 or 18 bits, because they need to hold the sum or difference of two 16-bit

Hi, Is there anything special I need to know about VP3's IDCT? I mean besides the fact that there are separate IDCTs to handle sparse coefficient matrices. Are the IDCT functions mathematically equivalent to any textbook IDCT functions? Thanks... -- -Mike Melanson --- >8 ---- List archives: http://www.xiph.org/archives/ Ogg project homepage: http://www.xiph.org/ogg/ To

Here http://lists.xiph.org/pipermail/theora/2004-September/000619.html Andrey describe encoder structure, this like: "I see the following structure of the compressor implemented in the FPGA (Xilinx Spartan 3 1000K gates): 1. Data from the external frame buffer (FB) memory goes to the Bayer-to-YCbCr (4:2:0) converter in overlapping 20x20 tiles that produce 6 8x8 blocks (one macroblock) on the

Dear R users, my search for a possibility to convert a generated model into VHDL to program an FPGA has still no solution. The problem: caret -> training -> model -> model.rds -> model.xml (PMML) --?--> VHDL-Code --?--> FPGA The (simplified) task: A photo detector with 16 channels is measuring the intensity of 16 different wavelength ranges. These data are classified with the

I'm not aware of an FPGA implementations yet. You could be the first! An encoder implementation would be much easier, because there are almost no rules about encoders. An encoder is free to behave any way it wants, so you could implement a very small subset of Opus and still have a compliant (and useful) encoder. A decoder implementation would be much harder, because decoders are required

Hi LLVM community members. I downloaded LLVM-GCC4.2 Front-end source code and succefully installed alongwith LLVM-2.3 on linux x86_64. I think it's front-end has better optimizations. I am naive to LLVM environment, my focus is to generate LLVM inermediate code for FPGA. Are there any resources/links/papers/documents which discusses LLVM intermediate generation for FPGA needs. I am aware

Hi all, Great news. On Thursday I finally play a video on FPGA. As I said the implementation is using the NIOS II processor. Andr? Costa is hard working to use the LEON processor. The video resolution is 96x80, because we have some FPGA internal memory constraints. I will try to use external memory to make possible decode a video of at least 320x240. The result can be see here: