similar to: Re: Theora cameras

Here http://lists.xiph.org/pipermail/theora/2004-September/000619.html Andrey describe encoder structure, this like: "I see the following structure of the compressor implemented in the FPGA (Xilinx Spartan 3 1000K gates): 1. Data from the external frame buffer (FB) memory goes to the Bayer-to-YCbCr (4:2:0) converter in overlapping 20x20 tiles that produce 6 8x8 blocks (one macroblock) on the

Andrey Filippov reports at his sourceforge website that he is 50% of the way towards the implementation of ogg theora in a FPGA, and has a goal of reaching 100% (leaving out motion compensation) by Dec. 14, 2004. These are some of the tasks he has completed most recently: Added 8-point forward DCT following the algorithm suggested in Theora specs. 2004-10-31 22:17 Created 2-d IDCT according

Andrey Filippov reports at his sourceforge website that he is 50% of the way towards the implementation of ogg theora in a FPGA, and has a goal of reaching 100% (leaving out motion compensation) by Dec. 14, 2004. These are some of the tasks he has completed most recently: Added 8-point forward DCT following the algorithm suggested in Theora specs. 2004-10-31 22:17 Created 2-d IDCT according

---------- Forwarded message ---------- From: digital design <developer.fpga at gmail.com> Date: 21 March 2011 13:38 Subject: Re: [theora] alghorithm of working encoder in libtheora To: bens at alum.mit.edu Cc: Reply-All at xiph.org On 18 March 2011 23:15, Benjamin M. Schwartz <bmschwar at fas.harvard.edu>wrote: > On 03/18/2011 01:44 PM, digital design wrote: > > Now i

Andrey posted the following update at his sourceforge web site. I'm sharing it here because I think it is fascinating to see the progress in his FPGA implemention of the Theora codec as it happens. John <snip> Wrote code and partially simulated compressor_two module with submodules. It gets fixed-width (12-bits) "pre-tokens" from the frame buffer in the coded order

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

I'm considering implementing the Theora format in the FPGA of the new camera. The previous model (Elphel 313 - http://www.elphel.com, https://sourceforge.net/projects/elphel) had smaller FPGA and was able to produce just motion JPEG utilizing 97% of the resources. The new (model 333) camera uses 3 times bigger FPGA (and also faster), it also has increased frame buffer and system memory.

Hello people My name is Felipe and I sent a proposal to the Google Summer of Code that the goal is to get a FPGA embeded system decoding Theora Streams in real-time. It was accepted and the mentor is the Ralph Giles. The proposal can be viewd here: http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt There is also a presentation with a better division of the

Thank, Timothy! I add this stages. About RLE: I have one more unresolved stage. Mike Melanson wrote in "VP3 Bitstream Format..." about RLE using: "* Zigzag Ordering: After transforming and quantizing a block of samples, the samples are not in an optimal order for run length encoding. Zigzag ordering rearranges the samples to put more zeros between non-zero samples." If we pass

Great news! Theora is running on FPGA. After almost a year of a great effort we have Theora validated on FPGA. Now I will try to integrated the hardware with a video controller to see the video! I completely implemented the ExpandBlock, CopyRecon, LoopFilter and UpdateUMVBorder functions. The ReconRefFrames function was partially implemented and the part before will run on a software compiled

Hi all, Great news. On Thursday I finally play a video on FPGA. As I said the implementation is using the NIOS II processor. Andr? Costa is hard working to use the LEON processor. The video resolution is 96x80, because we have some FPGA internal memory constraints. I will try to use external memory to make possible decode a video of at least 320x240. The result can be see here:

Theora hardware with LEON3 is runinng!!! My video was too slow, then I discovered that the problem was on LINUX! I don't exactly, but I suppose that the time of LINUX Call systems (like fread()) is the problem. If I don't use the linux (like is done on NIOS), I can to decode much faster than the time of exibition! Now we have two points on software (the hardware is the same,

Hi, The Integration with LEON (first part of my GSoC) is completed. http://atlas.lsc.ic.unicamp.br/~andre.lnc/theora_integration_with_leon3_full.png At the last week I had (leon3 + linux + libtheora) and (leon3 + send_vector_of_input + theora hardware) working ok. Firstly, I thougth that it just would be: http://atlas.lsc.ic.unicamp.br/~andre.lnc/theora_integration_with_leon3.png But it

Hello, First of all, I would like to say that my work that I wrote in the other email would be to do in hardware the functions: CopyRecon, LoopFilter and UpdateUMVBorder. These are modules that Leonardo had made, but it wasn't ok in FPGA. When I had a chat with Leonardo we were thinking in rewrite these module for to do this running in FPGA (to debug in a Hardware level is much more

Hi, I did some improvements and some bug corrections in Theora FPGA code. I'd like to post this new version in the SVN. How can I do that? Thanks -- Leonardo de Paula Rosa Piga Undergraduate Computer Engineering Student LSC - IC - UNICAMP http://www.students.ic.unicamp.br/~ra033956

Hi all, Does Theora Community have an interest in a multi-thread decoder implementation? I'm starting to work with multi-thread and I thought that Theora Decoder is a good choice for me, because I had been working with it in a FPGA implementation and I have experience with the library. I'm thinking in working with LoopFilter at first. Do you think I could start with it or there is a

Hello there, I'm a university student and our professor assigned us as a project to build a theora encoder/decoder. I need some help on some info that I didn't manage to find in Theora's reference. I am building a function that calculates motion estimation. When making motion estimations must I scan each and every macroblock in coded order? After that the motion vectors should be

Raphael, Some 15 years ago I implemented limited functionality Theora in our cameras FPGA (it took me 6 month of hard labor), and then gave up - it is a very crowded space and it is difficult to compete with more advanced codecs. And for our other work we anyway need almost raw image data, so we are using JPEG-based JP4 format (https://community.elphel.com/jp4) that we originally developed for

Good day! I'm creating HDL IP CORE (for using in FPGA) for theora encoder (now only I-frames). I don't undestand one moment. Now i develop such stages: 1. From RBG(byer) to YCbCr converter 2. DCT processing (8x8 pixels blocks) 3. Quantizator of DCT coeff. 4. Zig-Zag of quantized DCT coeff. and now i have uresolved last stage of compression - how i must send 8x8 blocks to huffman

Thanks! I was looking for the streamtranscoder and fopund it at your site. I wanted to convert for a test an OGG stream to OGG FLAC, but that doesn't seem to work. Could be it you never want to convert ogg to ogg flac (lossy to lossles makes no sense) so it is disabled? Anybody tried converting to flac stream? I wanted to use streamconverter, because it nicely reconnects every 10 seconds