similar to: Fix syscalls with more than four arguments on parisc

The parts of klibc specific to the parisc architecture. Signed-off-by: H. Peter Anvin <hpa at zytor.com> --- commit 078d6614054391efe17093f8d70340e2c0644ffb tree 63a4bf899e5ca2ef3c0a8e9ef3098273012f7a33 parent ebd2860ad3dc19cb11fd5b9cc235cab54e9165f4 author H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun 2006 16:58:36 -0700 committer H. Peter Anvin <hpa at zytor.com> Sun, 25 Jun

Implement "pid_t vfork(void)" for parisc. Signed-off-by: Kyle McMartin <kyle at parisc-linux.org> --- Ugh. vfork() me harder. Kbuild | 2 +- vfork.S | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/usr/klibc/arch/parisc/Kbuild b/usr/klibc/arch/parisc/Kbuild index d57a873..57ca5c2 100644 --- a/usr/klibc/arch/parisc/Kbuild

Hello Kyle, May be out of context but before I forget: > > + > > + /* store %r22 to errno... */ > > + ldil L%errno,%r1 > > + ldo R%errno(%r1),%r1 Could it not be 'load32 errno, %r1' (the assembly.h macro)? Cheers, Joel ---------- Club Scarlet : Tout le monde gagne! Si vous devenez aujourd'hui Scarlet One grace a un client existant de Scarlet, vous

parisc is currently passing argc as the second argument to __libc_init: --- crt0.S.old 2005-12-07 19:06:07.000000000 +0000 +++ crt0.S 2005-12-07 19:06:40.000000000 +0000 @@ -25,6 +25,10 @@ ldil L%$global$, %dp ldo R%$global$(%dp), %dp +/* Indicate that we don't need no stinkin' atexit callback */ + + ldi 0,%r25 + /* branch to __libc_init */

The PA-RISC ELF ABI puts the function pointer to be registered with atexit in %r23. Use this instead of passing in NULL. While it's unlikely to be used, doing the right thing is good. Signed-off-by: Kyle McMartin <kyle@parisc-linux.org> diff --git a/klibc/arch/parisc/crt0.S b/klibc/arch/parisc/crt0.S index 7428443..a9b6e96 100644 --- a/klibc/arch/parisc/crt0.S +++

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions

On 7/29/2017 1:28 AM, Dr. ERDI Gergo via llvm-dev wrote: > Hi, > > During instruction selection, I have the following code for certain > LOAD instructions: > > const LoadSDNode *LD = cast<LoadSDNode>(N); > SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), > VT, PtrVT, MVT::Other, > LD->getBasePtr(), LD->getChain()); >

Hi, I'd like to define a pseudo-instruction whose expansion will, as a side-effect, overwrite an input register's value: the pseudo-instruction ldw r1:r2, P to load 2 bytes from memory address P is to be expaneded to ld r1, P+ ld r2, P where "ld _, P+" is an instruction that loads a single byte from P, and post-increments P by one. How can I represent this behaviour in

Hello! I have the following simple IR: ================================== @l = common global i64 0, align 8 define void @hello() nounwind { entry: store i64 -4919131755279862989, i64* @l ret void } define i32 @main(i32 %argc, i8** %argv) nounwind { entry: call void @hello() %tmp = load i64* @l %conv = trunc i64 %tmp to i32 ret i32 %conv } ==================================

I am trying to prototype a back end for a new processor. It has a 64-bit datapath, so all registers are 64 bits and load instructions always extend to 64 bits. But the type 'int' is 32 bits, and arithmetic instructions have variants that operate on only the lower 32 bits of each register. So for a basic 'a = b + c' example, we get %0 = load i32, i32* @b, align 4, !tbaa !1 %1

Pipe's a strange syscall. Here is a fix for ia64. mh -- Martin Hicks Wild Open Source Inc. mort@wildopensource.com 613-266-2296 # This is a BitKeeper generated patch for the following project: # Project Name: The kernel C library # This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas: #

Hi Johannes, what processor are you targeting? Is it little-endian or big-endian? Ciao, Duncan. > I have the following simple IR: > > ================================== > @l = common global i64 0, align 8 > > define void @hello() nounwind { > entry: > store i64 -4919131755279862989, i64* @l > ret void > } > > define i32 @main(i32 %argc, i8** %argv)

On Sun, 28 May 2017, David Chisnall wrote: >> let Constraints = "@earlyclobber $reg" in >> def LDWRdPtr : Pseudo<(outs DREGS:$reg), >> (ins PTRREGS:$ptrreg), >> "ldw\t$reg, $ptrreg", >> [(set i16:$reg, (load i16:$ptrreg))]>, >>

Christian Sayer wrote: > Hi, > my target architecture has a kind of "16bit addressing mode", i.e. one address does not address 8 bit but a 16bit chunk. Consequently, every constant used to calculate effective addresses must be divided by two. > So far this is not such a problem for stack objects since FrameIndexes, function arguments etc. have a lot of custom lowering code where

Marcus Meissner did the ppc64 port, I did the update for crt0.S. Now ash does not segfault, at least. diff -p -purNx linux klibc-0.92.orig/Makefile klibc-0.92/Makefile --- klibc-0.92.orig/Makefile 2003-12-01 18:50:24.000000000 +0000 +++ klibc-0.92/Makefile 2003-12-12 23:18:23.000000000 +0000 @@ -20,4 +20,4 @@ clean: spotless: @set -e; for d in $(SUBDIRS); do $(MAKE) -C $$d $@; done - rm -f

Hi LLVMers, I'm writing a LLVM backend for C*Core, an ISA derived from Motorola M*Core. I was wondering if someone wrote some IR level optimization passes for backend porting before ISel, such as an IR transformation from GEP to integer conversion/calculating instructions, and PHI combination. Here's the bubble sorting example. The IR codes below are changed by hand and I try to write

Hi Bryan and other klibc people. I have taken a stamp on the Makefiles for klibc, this is what I came up with. 1) No longer recompile on every invocation 2) Correct checking on dependencies 3) Simpler makefile syntax (almost all over the place) I compile-time tested it only. Two open issues: a) Do we realy use .a files for initramfs. I renemed that to the executable. b) I renamed

On Wed, Sep 15, 2004 at 10:48:02AM +0930, Alan Modra wrote: > After using SHAREDFLAGS = -Ttext 0x0f000200 on ppc64 (which I see you > suggested in another email), I see the problem you're talking about. > > klibc is fundamentally broken on ppc64. You just can't call into > another chunk of code (klibc.so in this case) which has a separate toc > and expect things to

> > At first I thought this could be handled when lowering > loads and stores, but I realize that I can only catch the > targeted addresses of loads/stores here - however address > calculation nodes may occur anywhere in a DAG. > > > > So my first impulse would be to adjust the constants when > the GEP instructions are transformed to ADDs. Afaics his > would mean

The attached patches are against the v0.114 release and cover some of the tweaks I made while playing about testing ARM and Thumb support. Please review and consider applying. Even with the patches, ARM dynamic linking doesn't seem to work and the Thumb test applications seem to have shaken out a Thumb bug in the 2.4.21-rmk2 kernel which I'm still trying to track down. Still more fun to