similar to: architecture: "windows" reintegration/recovery

Hello On Wed, 2008-01-23 at 00:10 +0300, Nikita Danilov wrote: > Hello, > > below is a tentative list of tasks into which WBC effort can be > sub-divided. I also provided a less exact list for the EPOCH component, > and an incomplete list for the STL component. > > WBC tasks are estimated in lines-of-code with the total of (9100 + 3000) > LOC, where LOC is a non-comment,

Hi Nikita - This looks excellent, except that I don''t feel we have a good basis for the estimates yet. This has major architectural value as it gives a component breakdown and should be recorded as such on the architecture wiki. When you do these component breakdowns it is important to identify what interfaces are offered and used by the components (this is the static aspect of

> I''m not mad keen on propagating these sorts of asm atomic operations throughout > our code base. Other options would be: gcc has atomic builtins to do this kind of work. I don''t know about arm, but they do the job in x86 http://gcc.gnu.org/onlinedocs/gcc-4.1.1/gcc/Atomic-Builtins.html so atomic_inc(val) -> __sync_fetch_and_add(val, 1) and likewise for dec/sub Andres

Hello, Rlisters I have to compute p-values that are on the tail of the distribution, P-values < 10^-20. However, my current implementations enable one to estimate P-values up to 10^-12, or so. A typical example is found below, where t is my critical value. ########### example - code adapted from Rassoc ####################### rho01 = 0.5 rho105 = 0.5 rho005 = 0.5 t = 8 z = 2

All, If we can speculatively execute a load instruction, why isn’t it safe to hoist it out by promoting it to a scalar in LICM pass? There is a comment in LICM pass that if a load/store is conditional then it is not safe because it would break the LLVM concurrency model (See commit 73bfa4a). It has an IR test for checking this in test/Transforms/LICM/scalar-promote-memmodel.ll However, I have

Hi all, I'm working on a target whose registers have equal-sized subregisters and all of those subregisters can be named (or the other way round: registers can be grouped into super registers). So for instance we've got 16 registers W (as in wide) W0..W15 and 32 registers N (as in narrow) N0..N31. This way, W0 is made by grouping N0 and N1, W1 is N2 and N3, W2 is N4 and N5, ..., W15 is

Hi llvmdev! I've been working on adding coroutines to LLVM. Mentioned below is the implementation plan I'm following, for suggestions, flames and other input. Using segmented stacks is a prerequisite. The idea is to associate every coroutine with a coroutine descriptor. A coroutine descriptor consists of four words: w0, w1, w2 and w3. w0 always contains the _launcher_, and invoking a

On 07/28/2011 05:31 PM, Sanjoy Das wrote: > Hi llvmdev! > > I've been working on adding coroutines to LLVM. Mentioned below is the > implementation plan I'm following, for suggestions, flames and other > input. Using segmented stacks is a prerequisite. I think my only comment is that, while this would probably work, implementing it in C with a bit of assembly for

I think gcc is right. It inserted a branch for n == 0 (the cbz at the top), so that's not a problem. In all other regards, this is safe: if you examine the sequence of loads and stores, it eliminated all but the first load and all but the last store. How's that unsafe? If I had to guess, the bug here is that LLVM doesn't want to hoist the load over the condition (which it is right

Thanks for the background on the concurrent memory model. So, is it sufficient that the loop entry is guarded by condition (cbz at top) for preventing the race? The loop entry will be guarded by condition if loop has been rotated by loop rotate pass. Since LICM runs after loop rotate, we can use ScalarEvolution::isLoopEntryGuardedByCond to check if we can speculatively execute load without

Hi, Jiong, Thanks for the patch! It is a great start to support 32bit register in BPF. In the past, I have studied a little bit to see whether 32bit register support may reduce the number of unnecessary shifts on x86_64 and improve the performance. Looking through a few bpf programs and it looks like the opportunity is not great, but still nice to have if we have this capability. As you

Move I/O instruction building to the sub-arch layer. Some very crafty but esoteric macros are used here to get optimized native instructions for port I/O in Linux be writing raw instruction strings. Adding a wrapper layer here is fairly easy, and makes the full range of I/O instructions available to the VMI interface. Also, slowing down I/O is not a useful operation in a VM, so there is a VMI

Move I/O instruction building to the sub-arch layer. Some very crafty but esoteric macros are used here to get optimized native instructions for port I/O in Linux be writing raw instruction strings. Adding a wrapper layer here is fairly easy, and makes the full range of I/O instructions available to the VMI interface. Also, slowing down I/O is not a useful operation in a VM, so there is a VMI

Good day, some time ago we discussed that it would be very helpful to store epoch in inode on mds. the perfect solution could be to store epoch in old inode body, but there is no much space for this in the body and with DMU we''ll have this problem again. given the minimal inode size we use on MDS is 512 bytes, we can store upto 13 stripes in the body. larger EAs go to a dedicated block.

Hello, First of all I am french, so please forgive me, if there are some big language mistakes in my sentences. I think, it is the good mail address to send my question, if not please tell me and forgive me. I am working on a project, and I use the nnet library. Our customers do not want us to install R on their machine, so we just use R for making the training of our neurons network. This

Hello, First of all I am french, so please forgive me, if there are some big language mistakes in my sentences. I do not know if it is the good mail address to send my question, if not please tell me and forgive me, I have also sent this quetion to r-help, because the answer could be known from the programmers and the other R users :). I am working on a project, and I use the nnet library.

As you may have noticed, we released a 64b S4 chip that runs an ILP32 variant of the AArch64 ABI, and now we'd like to upstream that work. I've pushed preliminary patches to https://github.com/TNorthover/llvm-project/pull/1/commits (arm64_32 branch in that repo) to accompany this RFC. The changes divide fairly neatly into three categories. First, there's AArch64 ILP32 support, which

Is there s written procedure how to reintegrate a nod of a 2-node cluster after complete reinstallation of the OS ? Cheers, M

hi all i'm new to the area of neural networks. i've been reading some references and seem to understand some of the learning algorithms. i am very familiar with regression and would just like to see how neural nets handle this problem so i've been using the nnet package. i simply want to use a 3 layer neural net, ie 1 input, 1 hidden layer (where the hidden layer is linear, since i

Currently the AtomicExpandPass will lower the following IR: define i1 @foo(i32* %obj, i32 %old, i32 %new) { entry: %v0 = cmpxchg weak volatile i32* %obj, i32 %old, i32 %new _*release acquire*_ %v1 = extractvalue { i32, i1 } %v0, 1 ret i1 %v1 } to the equivalent of the following on AArch64: _*ldxr w8, [x0]*_ cmp w8, w1 b.ne .LBB0_3 // BB#1: