similar to: strange apparently data-dependent crash with large data (PR#6955)

Displaying 20 results from an estimated 2000 matches similar to: "strange apparently data-dependent crash with large data (PR#6955)"

2009 Jun 08
1
Random Forest % Variation vs Psuedo-R^2?
Hi all (and Andy!), When running a randomForest run in R, I get the last part of an output (with do.trace=T) that looks like this: 1993 | 0.04606 130.43 | 1994 | 0.04605 130.40 | 1995 | 0.04605 130.43 | 1996 | 0.04605 130.43 | 1997 | 0.04606 130.44 | 1998 | 0.04607 130.47 | 1999 | 0.04606 130.46 | 2000 | 0.04605 130.42 | With the first column representing the
2006 Apr 30
1
Number of Clusters
Dear R users, I am interested in clustering in R. In SAS we have some criteria for determining the number of clusters using the PROC CLUSTER procedure, which are "CCC" cubic clustering criterion (Sarl 1981), Psuedo F (PSF), and Psuedo T square (PST). My question is do thsese criterion exists in R, I tried to search and got one hit (BIC) in Mclust, which I am aware of, any input is
2010 Aug 26
0
[LLVMdev] What does this error mean: psuedo instructions should be removed before code emission?
On Aug 26, 2010, at 10:50 AM, Yuri wrote: > Also there is a typo: it probably should read pseudo. A pseudo instruction is used internally without llvm, but it does not correspond directly to a real instruction in the target architecture. Before emitting the final compiled code, all the pseudo instructions must be expanded to real instructions. If you're seeing that error, it means that
2002 Apr 02
1
Extract psuedo model matrix from nls?
Hi R-list, I'd like to extract the psuedo model matrix (derivative of fitted values wrt the parameters) from an nls object. Any suggestions? Thanks, Murray Jorgensen Dr Murray Jorgensen on leave from: Mathematics and Statistics Department of Statistics University of Victoria University of Waikato PO BOX 3045 STN CSC Hamilton, New Zealand
2008 Oct 27
3
[LLVMdev] ADDE on HW that doesn't have flags?
The language I'm targeting doesn't have flags; I'd like to implement ADDE as a macro or psuedo-instruction that takes 3 parameters and returns 2. In my InstrInfo.td file, tablegen complains if I try to define multiple return values; adde is defined in TargetSelectionDAG.td to be a binary op that takes an extra flag in and sends an extra flag out. I tried to custom lower ADDE
2009 Jun 12
6
[LLVMdev] Bug in x86 JIT fast emitter.
Hi there, I think I've found a bug in the x86 JIT. I get an assertion failure when using thread-local variables and the fast emitter. It only happens with the JIT, the fast emiiter and thread-locals. (The IR passes the verifier) Here's the failure: X86CodeEmitter.cpp:516: void<unnamed>::Emitter::emitInstruction(const llvm::MachineInstr&, const llvm::TargetInstrDesc*):
2013 Nov 23
2
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
Amara, first, thank you for answering. but I found expandPsuedo instructions actually happens before post-RA, like the following code showing: your approach is a little hacky, right? : ) // Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); printAndVerify("After ExpandPostRAPseudos"); // Run pre-sched2 passes. if (addPreSched2())
2017 Nov 20
2
[PATCH] Fix memory issue in Projection API
Hello, Attached is a patch to resolve a memory issue using the Projection API when compiling using a psuedo-stack / limited memory. Please let me any ?s you might have. Cheers, Drew -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.xiph.org/pipermail/opus/attachments/20171120/84e36e1b/attachment-0001.html> -------------- next part --------------
2008 Dec 17
2
[LLVMdev] Shifts that use only 5 LSBs.
On Dec 16, 2008, at 7:57 PM, Eli Friedman wrote: > On Tue, Dec 16, 2008 at 3:36 PM, Daniel M Gessel <gessel at apple.com> > wrote: >> I'm working on a Target that only uses the 5 lsbs of the shift >> amount. > > Okay, that's quite common... x86 is the same. > Thanks - yes, I'd heard rumors that x86 operates the same way. >> I only have 32
2009 Jan 13
9
Updating multiple databases at the same time
I have an application that is load balanced. I have a master database which I update once a day. Then I push the raw mysql files to all other servers so they are the same as the master. This works fine, but there are a few situations where I need all databases to update in real-time. What would be the best way to achieve this in rails? Here is an example of what I am trying to do. I want to
2020 Nov 19
2
[RFC] Intel AMX programming model
Hi, Several months ago, we have some discussion for Intel AMX programming model in llvm-dev. H.J. post the AMX ABI at [1], and I sent the design for the programming model at [2]. Thank Hal, Philip for the time to review the design and provide good ideas to improve the design. After that I implemented the patch [4] and it is reviewed in LLVM community. The patch covers 6 components. 1. The c
2009 Jun 12
2
[LLVMdev] Bug in x86 JIT fast emitter.
Evan, Any plans to add it any time soon? It would be really appreciated. Evan Cheng wrote: > X86 JIT does not yet support TLS. > > Evan > On Jun 12, 2009, at 2:48 AM, Mark Shannon wrote: > >> Hi there, >> >> I think I've found a bug in the x86 JIT. I get an assertion failure >> when >> using thread-local variables and the fast emitter.
2008 Dec 17
0
[LLVMdev] Shifts that use only 5 LSBs.
On Tue, Dec 16, 2008 at 5:20 PM, Daniel M Gessel <gessel at apple.com> wrote: > The problem here is that it looks like LLVM is introducing an expansion that > assumes 32 bit shifts use more than 5 bits of the shift value. > I created a simple test function: > u64 mebbe_shift( u64 x, int test ) > { > if( test ) > x <<= 2; > return x; > } > I compile using
2010 Nov 14
1
[LLVMdev] Pesudo X86 instructions used for generating constants
Hi, I noticed a bunch of psuedo instructions used for creation of constants without generating loads. e.g. pxor xmm0, xmm0 Here is an example of what i am referring to snipped from X86InstrSSE.td: def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "", [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>, TB, OpSize; My question is
2009 Nov 03
1
dahdi channel not showing up
Hi, I have a X101P card and am running Asterisk SVN-trunk-r226890. The X101P card seems to be identified properly: debian:/usr/src/dahdi-tools# dahdi_hardware pci:0000:01:01.0 wcfxo+ e159:0001 Wildcard X101P debian:/usr/src/dahdi-tools# dahdi_cfg -vv DAHDI Tools Version - SVN-trunk-r7409 DAHDI Version: SVN-trunk-r7445 Echo Canceller(s): MG2 Configuration ======================
2017 Jun 02
1
modEvA D-squared for gamma glm
Hi All, I am running a generalized linear model with gamma distribution in R (glm, family=gamma ) for my data (gene expression as response variable and few predictors). I want to calculate r-squared for this model. I have been reading online about it and found there are multiple formulas for calculating R2 (psuedo) for glm (in R) with gaussian (r2 from linear model), logistic regression
2008 Oct 27
0
[LLVMdev] ADDE on HW that doesn't have flags?
On Mon, Oct 27, 2008 at 10:11 AM, Daniel M Gessel <gessel at apple.com> wrote: > The language I'm targeting doesn't have flags; I'd like to implement > ADDE as a macro or psuedo-instruction that takes 3 parameters and > returns 2. > > In my InstrInfo.td file, tablegen complains if I try to define > multiple return values; adde is defined in TargetSelectionDAG.td
2007 May 02
1
[LLVMdev] Instruction Scheduling in LLVM
Hello, I am working with the SelectionDAG/ScheduleDAG framework to implement a variation of the List scheduling Algorithm in LLVM. I was trying to understand the existing List scheduler implementation in LLVM. I have a doubt about the SUnits structure which contain flagged nodes together. The instructions within a Sunit are scheduled as a single unit. My understanding is that the nodes in the
2009 Jun 12
0
[LLVMdev] Bug in x86 JIT fast emitter.
X86 JIT does not yet support TLS. Evan On Jun 12, 2009, at 2:48 AM, Mark Shannon wrote: > Hi there, > > I think I've found a bug in the x86 JIT. I get an assertion failure > when > using thread-local variables and the fast emitter. > It only happens with the JIT, the fast emiiter and thread-locals. > (The IR passes the verifier) > > Here's the failure: >
2011 May 12
1
Simple 95% confidence interval for a median
Hi! I have a data set of 86 values that are non-normally distributed (counts). The median value is 10. I want to get an estimate of the 95% confidence interval for this median value. I tried to use a one-sample Wiolcoxin test: wilcox.test(Comps,mu=10,conf.int=TRUE) and got the following output: Wilcoxon signed rank test with continuity correction data: Comps V = 2111, p-value = 0.05846