Displaying 9 results from an estimated 9 matches similar to: "[PATCH 1/2] drm/nouveau/pm: Prepare for more GDDR5 MR values"
2013 Jul 18
1
[PATCH 02/11] drm/nv50/pm: Fix last timing register in NVA3+, fix typo in NV50
Also fix some timings for NVA0
Signed-off-by: Roy Spliet <r.spliet at student.tudelft.nl>
---
drivers/gpu/drm/nouveau/nouveau_mem.c | 45 +++++++++++++++++++----------------
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 4f6a572..35b5858 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
2013 Jul 18
0
[PATCH 02/11] drm/nv50/pm: Fix last timing register in NVA3+, fix typo in NV50
Whoops, ignore this patch, wrong one.
Op 18-07-13 13:58, Roy Spliet schreef:
> Also fix some timings for NVA0
>
> Signed-off-by: Roy Spliet <r.spliet at student.tudelft.nl>
> ---
> drivers/gpu/drm/nouveau/nouveau_mem.c | 45 +++++++++++++++++++----------------
> 1 file changed, 25 insertions(+), 20 deletions(-)
>
> diff --git
2014 Sep 29
18
Implement reclocking for DDR2, DDR3, GDDR3
Following a series of patches that implement memory reclocking for NVA3/5/8 with
DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics
cards, but I expect reclocking now to work on many more.
Testers can pick up these patches and test it by enabling pstate
(nouveau.pstate=1). They should then be able to change clocks by writing to
/sys/class/drm/card0/device/pstate. Correct
2014 Aug 25
12
[PATCH envytools] demmio: Add decoding of some MEM_TIMINGS registers for NVC0.
---
rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml
index 500cea9..e006dbe 100644
--- a/rnndb/memory/nvc0_pbfb.xml
+++ b/rnndb/memory/nvc0_pbfb.xml
@@ -49,23 +49,54 @@
Most bitfields are unknown.
</doc>
<bitfield high="7"
2017 Apr 10
0
[PATCH 08/11] nvkm/ramgt215: Add train ptrn upload for GDDR5
Signed-off-by: Roy Spliet <nouveau at spliet.org>
Tested-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h | 1 +
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 128 +++++++++++++++++-----
2 files changed, 99 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h
2017 Apr 10
0
[PATCH 03/11] nvkm/gddr5: MR calculation for timing table v1.0
Merges in skeggsb's:
"fb/ram/gf10x: timing_10_0e_30"
Todo:
- find l3, rq
- triple-check
Signed-off-by: Roy Spliet <nouveau at spliet.org>
---
.../drm/nouveau/include/nvkm/subdev/bios/ramcfg.h | 12 +++---
drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c | 22 ++++++++--
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 2 +
2015 Oct 12
2
fixing GDDR5 reclocking on kepler cards
this is my first patch on the list through git send-mail and I hope everything
is set up right, sorry for the noise here, but I don't want to try with an
empty mail :)
as the subject already says, this patch fixes one of the more serious issues
while reclocking gddr5 on kepler cards. It works for me and for a bunch of others
I met on IRC.
Karol Herbst (1):
pll/gk104: fix PLL instability
2014 Aug 25
0
[PATCH envytools] demmio: Add decoding of some MEM_TIMINGS registers for NVC0.
On 25/08/2014 20:58, Christian Costa wrote:
> ---
> rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++---
> 1 file changed, 34 insertions(+), 3 deletions(-)
>
> diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml
> index 500cea9..e006dbe 100644
> --- a/rnndb/memory/nvc0_pbfb.xml
> +++ b/rnndb/memory/nvc0_pbfb.xml
> @@ -49,23 +49,54 @@
2013 Jun 25
8
[Bug 66176] New: nouveau.perflvl kernel parameter doesn't work
https://bugs.freedesktop.org/show_bug.cgi?id=66176
Priority: medium
Bug ID: 66176
Assignee: nouveau at lists.freedesktop.org
Summary: nouveau.perflvl kernel parameter doesn't work
QA Contact: xorg-team at lists.x.org
Severity: normal
Classification: Unclassified
OS: All
Reporter: mr.dash.four at