similar to: NIC has IP, but has "no carrier"

heya i've been using freebsd's ipfw for quite a while and recently on a new server i've got this issue with ipfw that i can't understand ... something is wrong ... 01000 8042 1947866 allow ip from any to any via fxp0 01010 0 0 allow ip from any to any via lo0 01014 9886 4170269 divert 8668 ip from any to any in via vr0 01015 0 0 check-state 01130 14679 5695969 skipto 1800 ip from

On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >> Jeff Bush <jeffbush001 at gmail.com> writes: >> >>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >>> %sum = fadd %tx, %ty >>> %newvalue

Hi, there I am writing an backend, and I met a problem. We don't have load/store instructions for vector predicate registers(vpr for short). The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr. vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations. A vr has 512 bits, and

Hi, I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands. If I use virtual registers, do I need to mark them as "early clobber"? I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend. What is the effect of marking a

. and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier.. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Friday, December 02, 2011 2:40 PM To: LLVM Dev Subject: [LLVMdev]

On Dec 2, 2011, at 2:41 PM, Sergei Larin wrote: > … and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier…. Isn't that just the order of the instructions in the list? I don't see anything that prevents getting the order of instructions. It might require iterator over MIs in the packet. But for

Evan, I will need to comprehend it better, but one small comment right away. Did we not discuss one more option for bundle implementation - global cycle ID. We would add an unsigned int field to MI definition representing "global scheduling cycle". All MIs with the same global cycle value belong to one group/packet. Zero means unscheduled MI. That is light weight,

Hi Evan, I just read your proposal and the following discussion for VLIW support and want to share my experience of writing a VLIW back-end for LLVM. I would not integrate the packetizer into the register allocator super class since it would reduce the flexibility for the back-end developer to add some optimization passes after the packetizer. Instead, I would add the packetizer as a separate

Hi all, Can anyone give an idea to solve my problem? I'm implementing backend part using LLVM for my research architecture. The main issue is that this architecture cannot use stack/heap. So, all the value should be stored in the register. Given that architecture, load/store instruction in IR uses virtual register to load/ store the value. For example: C source code is: if(...) { a = 1;

i had such problems on my mini-ITX. when sharing irq's with video or sound card, network traffic during ogg playing (for example on nfs) or quick moving windows crashed the interface. ifconfig down/up resolved the problem. it has been solved for a while now (i couldn't reproduce this problem) i think. regards, OLivier Le Jeudi 12 D?cembre 2002 03:45, The Anarcat a ?crit : >

Hi ! First of all, I am sorry if this is not the list for that, but I've been learning (a little bit...) a way to implement a freeBSD firewall. So far I came up with a set of rules I would like to show you for commenting. I am sure there're a lot of errors and/or stupid rules (I am not sure the rules order is good for what I need) and I would be really pleased if one could have a look

On Wed, Aug 07, 2013 at 08:04:13PM -0700, Sudeep Dutt wrote: > From: Caz Yokoyama <Caz.Yokoyama at intel.com> > > This patch introduces a sample user space daemon which > implements the virtio device backends on the host. The daemon > creates/removes/configures virtio device backends by communicating with > the Intel MIC Host Driver. The virtio devices currently supported

On Wed, Aug 07, 2013 at 08:04:13PM -0700, Sudeep Dutt wrote: > From: Caz Yokoyama <Caz.Yokoyama at intel.com> > > This patch introduces a sample user space daemon which > implements the virtio device backends on the host. The daemon > creates/removes/configures virtio device backends by communicating with > the Intel MIC Host Driver. The virtio devices currently supported

Ah, I think I get it now. This was mentioned earlier in the thread, but it didn't click at the time. It sounds like I can do instruction selection with a pattern like (omitting selection of the sources): let Constraints = "$dst = $oldvalue" in { def MASKEDARITH : MyInstruction< (outs VectorReg:$dst), (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,

Machine Instruction Bundle in LLVM Hi all, There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community. Design Criteria 1. The

Hello, Freebsd-stable. BIND on my new router (7.1-STABLE, BIND 9.4.3-P1) shows bunch of errors on every start and doesn't answer on requests for 30-60 seconds after that. Errors are like this: Jan 24 12:18:12 gateway named[1455]: /usr/src/lib/bind/isc/../../../contrib/bind9/lib/isc/unix/socket.c:1567: unexpected error: Jan 24 12:18:12 gateway named[1455]: internal_send: 193.0.14.129#53:

On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on whether

On Dec 2, 2011, at 12:40 PM, Evan Cheng wrote: > There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community. Let me add some

Running freeBSD 6.1 After changing chkrootkit to the latest version V. 0.47 and compiling it then running it I get the following: ==================<SNIPPIT>================ Searching for anomalies in shell history files... nothing found Checking `asp'... not infected Checking `bindshell'... INFECTED (PORTS: 6667) Checking `lkm'... You have 131 process hidden for readdir

Endianness issues are now consistent as per the documentation in host/mic_virtio.h. Note that the host can be both BE or LE whereas the card is always LE. Memory space sparse warnings are fixed for now by using __force. This is sufficient for now since the driver depends on x86 but will need to be revisited if we support other architectures which treat I/O memory differently from system memory.